Thursday, November 22nd 2018, Vivienne Sze, Associate Professor at MIT in the Electrical Engineering and Computer Science Department, is presenting “Energy-Efficient Edge Computing for AI-driven Applications”. Day & Time: Thursday November 22nd, 2018 4:10 p.m. ‐ 5:00 p.m. Speaker: Vivienne Sze Associate Professor, MIT in the Electrical Engineering and Computer Science Department Organizers: IEEE Toronto Solid-State Circuits Society Location: Sanford Fleming Building, Room 1105 10 King’s College Rd Toronto, Ontario Canada M5S 3G4 Contact: Dustin Dunwell Abstract: Edge computing near the sensor is preferred over the cloud due to privacy and/or latency concerns for a wide range of applications including robotics/drones, self-driving cars, smart Internet of Things, and portable/wearable electronics. However, at the sensor there are often stringent constraints on energy consumption and cost in addition to throughput and accuracy requirements. In this talk, we will describe how joint algorithm and hardware design can be used to reduce energy consumption while delivering real-time and robust performance for applications including deep learning, computer vision, autonomous navigation and video/image processing. We will show how energy-efficient techniques that exploit correlation and sparsity to reduce compute, data movement and storage costs can be applied to various AI tasks including object detection, image classification, depth estimation, super-resolution, localization and mapping. Biography: Vivienne Sze is an Associate Professor at MIT in the Electrical Engineering and Computer Science Department. Her research interests include energy-aware signal processing algorithms, and low-power circuit and system design for portable multimedia applications, including computer vision, deep learning, autonomous navigation, and video process/coding. Prior to joining MIT, she was a Member of Technical Staff in the R&D Center at TI, where she designed low-power algorithms and architectures for video coding. She also represented TI in the JCT-VC committee of ITU-T and ISO/IEC standards body during the development of High Efficiency Video Coding (HEVC), which received a Primetime Emmy Engineering Award. She is a co-editor of the book entitled “High Efficiency Video Coding (HEVC): Algorithms and Architectures” (Springer, 2014). Prof. Sze received the B.A.Sc. degree from the University of Toronto in 2004, and the S.M. and Ph.D. degree from MIT in 2006 and 2010, respectively. In 2011, she received the Jin-Au Kong Outstanding Doctoral Thesis Prize in Electrical Engineering at MIT. She is a recipient of the 2018 Facebook Hardware & Software Systems Research Award, the 2017 Qualcomm Faculty Award, the 2016 Google Faculty Research Award, the 2016 AFOSR Young Investigator Research Program (YIP) Award, the 2016 3M Non-Tenured Faculty Award, the 2014 DARPA Young Faculty Award, the 2007 DAC/ISSCC Student Design Contest Award, and a co-recipient of the 2017 CICC Outstanding Invited Paper Award, the 2016 IEEE Micro Top Picks Award and the 2008 A-SSCC Outstanding Design Award. For more information about research in the Energy-Efficient Multimedia Systems Group at MIT visit: http://www.rle.mit.edu/eems/

Monday December 17th, 2018 at 1:10 p.m. Dr. Sorin Voinigescu, Professor at the University of Toronto, will be presenting a SSCS distinguished lecture: “The Qubit is the Transistor: Si-based Transistor and Analog-Mixed-Signal Circuit Scaling and the Natural Progression of Moore’s Law to Silicon Quantum Computing at the Atomic Scale”. Day & Time: Monday December 17th, 2018 1:10 p.m. ‐ 2:30 p.m. Speaker: Dr. Sorin Voinigescu Professor, University of Toronto Organizers: SSCS IEEE Toronto Location: Bahen Centre, Room BA1230 40 St George St, Toronto, ON M5S 2E4 Contact: Dustin Dunwell Abstract: Quantum computing is a hot topic at very cool temperatures. Cool as in 10-100 mK. Recently, a cold-atom physicist nonchalantly asked me the question: Why are you interested in high temperature quantum computers? High as in 4 -12 K. He was serious! Need I talk about Global Warming in such cool environments? Pluto is another option. Today, quantum computers consist of racks of microwave and analog-mixed-signal test equipment, FPGAs and feedback loops for error correction, long 50-Ohm coaxial cables, and a few qubits formed with non-linear Josephson-junction resonators, entangled through niobium superconducting λ/4 resonators at 8-20 GHz, biased by a DC magnetic field of up to 1 Tesla, and whose spin is controlled by an AC magnetic field rotating in the “lab frame”. Are you still spinning? There’s talk of electrons as “microwave photons”, Larmor and Rabi frequencies, photon-to-spin entanglement, RAP (as in rapid adiabatic passage), Bloch sphere, tensors in n-dimensional Hilbert spaces, but also of OFDM, phase noise, I-Q up- and down- conversion, Gaussian pulse modulation, coherent π/2, π/4 spin phase rotations in azimuth and elevation. Qubits are logic gates and memory cells at the same time. Logic gate operations consist of synchronized microwave pulses applied sequentially to the same qubits. The only probabilistic part (need I mention Schrodinger’s cats Flip and Flop?) is readout, when the spin state is projected on the Z (DC magnetic field) axis! In other words, quantum computing is about everything you learned and thought you’d never use again, should have learned, or you were never taught in undergrad and grad school in math, quantum and atomic physics, electronics, electromagnetics, and computer science… This talk will first attempt to demystify and translate the physics of quantum computing to an electronics engineer jargon. Next, I will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and explore their scalability through simulation to 2nm dimensions, when the coupling energy, ΔE, becomes comparable to thermal noise at 77-300 K. Silicon electron-spin and hole-spin coupled quantum-dot (QD) qubits have attracted a lot of interest recently due to their potential for integration in commercial CMOS technology. However, like their more established superconducting cousins, to date, because of the low confinement and coupling energies (e.g. ΔE, in the tens of μeV range, comparable to the thermal noise level, kBT, at 100 mK) their operation has been restricted to temperatures below 100 mK. Moreover, since cryogenic systems cannot remove more than a few μW of thermal power at 100 mK, and the experimental laboratory (think TNC at U of T versus TSMC 7nm fab) technologies in which these qubits have been realized do not allow for fabrication of spin manipulation and readout circuitry, the latter reside on a separate chip, at 4 K or higher temperature. The lack of monolithic integration further degrades readout fidelity and computing speed because the atto-Farad capacitance, high-impedance qubit needs to drive 50Ω and 100x larger capacitance interconnect off- chip. A qubit with higher confinement and coupling energies, with spin resonance in the upper mm-wave region, will allow for higher temperature operation, alleviating these problems and enabling large-scale monolithic quantum computing processors. For example, a qubit operating at 4 K would require mode splitting energies of 0.25 meV which corresponds to a spin resonance frequency of 60 GHz and require a DC magnetic field of 2.5 T. Simplifying a bit, 240GHz spin-resonance frequencies and 9T magnetic fields should be adequate for 12K operation and 1.4 THz with an humongous magnetic field are needed for 77 K. You get the drift… Finally, I will briefly review hot-off-the-press results obtained here at U of T. For the first time we report (i) integration of qubits and electronics on the same die, (ii) strained SiGe hole-spin and strained Si electron-spin FDSOI qubits on the same die, and (iii) propose a monolithic processor architecture which allows for short, 10-20ps spin control pulses and high Rabi frequencies, fRabi, to compensate for short spin phase coherence lifetime. We also demonstrate that, at 2 K, MOSFETs and cascodes can be operated as QDs in the subthreshold region while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively. If we still have holiday time left, I will go through a tutorial example of how we can derive the specification for the mm-wave spin manipulation and readout circuits starting from the Hamiltonian and the measured I-V characteristics of our SiGe hole-spin qubits. I may touch on the impact of minimum-size (18nmx6nmx80nm) MOSFET ofset voltage and process variation on qubit characteristics, on spin manipulation and readout architectural options (low phase-noise radar, OFDM radio, low-noise, broadband, ultra-high-gain TIAs), mm-wave switch impact and OFDM sub-carrier spacing on qubit crosstalk and isolation…Or maybe we should leave that for New Years’.