Solid-State Circuits

Tuesday August 8, 2017 at 4:10 p.m. Dr. Shanthi Pavan, Professor of Electrical Engineering at the Indian Institute of Technology, will be presenting “Design Considerations for Power Efficient Continuous-Time Delta Sigma ADCs”. Recording of the Event: https://drive.google.com/file/d/0B5wB8uI08dYvbmtnQjJoclF0VW8/view?usp=sharing Day & Time: Tuesday August 8, 2017 4:10 p.m. – 5:10 p.m. Speaker: Dr. Shanthi Pavan Professor of Electrical Engineering Indian Institute of Technology, Madras Location: Bahen Centre, room BA1230 40 St George St, Toronto, ON M5S 2E4 Contact: Dustin Dunwell Organizers: Solid-State Circuits Society Abstract: Continuous-time Delta-Sigma Modulators (CTDSMs) are a compelling choice for the design of high resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices, many of which seem to pull in opposite directions. Further, it is often difficult to make a clear comparison of various architectures, as they have been designed for dissimilar specifications, by different design groups, and in different technology nodes. This talk examines various design alternatives for the design of power efficient single-loop continuous-time delta sigma converters. Biography: Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engineering from the Indian Institute of Technology, Madras in 1995 and the Masters and Doctoral degrees from Columbia University, New York in 1997 and 1999 respectively. He is now with the Indian Institute of Technology-Madras, where he is a Professor of Electrical Engineering. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr.Pavan is the recipient of many awards for teaching and research, including the IEEE Circuits and Systems Society Darlington Best Paper Award and the Shanti Swarup Bhatnagar Award (from the Government of India). He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I – Regular Papers. He is a Fellow of the Indian National Academy of Engineering.

Friday June 9, 2017 at 2:10 p.m. IEEE Distinguished Lecturer and Professor at Lund University Pietro Andreani will be presenting “RF Integrated Harmonic Oscillators in Silicon Technologies”. Event Media: Event Slides Recording of the Event Day & Time: Friday June 9, 2017 2:10 p.m. – 3:30 p.m. Speaker: Dr. Pietro Andreani Professor, Lund University IEEE Distinguished Lecturer and Professor Location: University of Toronto 40 St. George Street Toronto, Ontario Canada, M5S 2E4 Bahen Center of Information Technology Room Number: B024 Free for everyone. Complimentary refreshments will be provided. Contact: Dustin Dunwell Organizers: Solid State Circuits Society Abstract: As one of the truly fundamental analog functions in any wireless/wireline application, the voltage-controlled oscillator keeps attracting a great deal of well-deserved attention. In this presentation, we will investigate the mechanisms of phase noise generation in harmonic oscillators, including some recently published general results, after which we will analyze both classical and emergent oscillator architectures, describing pros and cons for each. Various techniques to achieve a very wide oscillator tuning range will be illustrated as well. Biography: Pietro Adreani received the M.S.E.E. degree from the University of Pisa, Italy, in 1988, and the Ph.D. degree from Lund University, Sweden, in 1999. Between 2001 and 2007 he was chair professor at the Center for Physical Electronics, Technical University of Denmark. From 2005 to 2014 he had a 20% position as analog/RF designer at Ericsson AB in Lund, Sweden. Since 2007, he has been associate professor at the department of Electrical and Information Technology (EIT), Lund University, working analog/mixed-mode/RF IC design. He is also the head of the VINNOVA Center for System Design on Silicon, hosted by EIT. He has been a TPC member of ISSCC (2007-2012), is a TPC member of ESSCIRC (chair of the Frequency Generation subcommittee since 2012, TPC chair in 2014) and RFIC, and Associate Editor of JSSC. He has been an IEEE SSCS Distinguished Lecturer since 2017. He has authored numerous papers on harmonic oscillators and phase noise.

Monday April 24, 2017 at 2:10 p.m. Dr. Azita Emami, Professor of Electrical Engineering and Medical Engineering at Caltech, will be presenting a distinguished lecture, “Holistic Design in Optical Interconnects”. Day & Time: Monday, April 24th, 2017 2:10 p.m. – 3:30 p.m. Speaker: Dr. Azita Emami Professor of Electrical Engineering and Medical Engineering Heritage Medical Research Institute Investigator Deputy Chair of Division of Engineering and Applied Sciences Caltech Location: Room B024, Bahen Centre 40 St. George Street, Toronto, ON M5S 2E4 Contact: Dustin Dunwell Organizers: IEEE Toronto SSCS Cost: Free for everyone. Complimentary refreshments will be provided. Abstract: The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption, performance and size spectra. Today Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented. Biography: Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007, she was an Assistant Professor of Electrical Engineering at Columbia University in the city of New York. In 2007, she joined Caltech, where she is now a Professor of Electrical Engineering and Medical Engineering. She is a Heritage Medical Research Institute Investigator, and serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems, high-speed on-chip and chip-to-chip interconnects, system and circuit design solutions for highly-scaled CMOS technologies, wearable and implantable devices for neural recording, stimulation, and efficient drug delivery.