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  • Integrated Broadband Analog Delay Circuits

    Toronto, Canada

    Recording: Click here to view Part I of the talk. The humble analog delay is simple in principle but complicated in practice. Analog delays are useful in analog filters, distributed amplifiers, and time-interleaved or pipelined analog signal processing. Unfortunately, it can be quite tricky to delay a continuous-time broadband analog waveform without distortion on an integrated circuit! Over the past two decades, our lab has repeatedly encountered the need for integrated broadband analog delays and has done much work on their implementation. Now that CMOS technologies can readily process analog signals with 10’s of GHz of bandwidth, analog delays less than one nanosecond are being used in new and creative ways. This talk reviews delay approximation and the implementation of delays from 10’s to 100’s of picoseconds having bandwidths up to 10’s of GHz. Case studies are presented using the analog delay circuits in FIR and IIR filters for wireline transceivers and in high-speed data converters. Part I Date: 10 Mar 2021 Time: 04:10 PM to 05:00 PM Location: Virtual Organizer(s): IEEE Toronto SSCS Contact: Toronto Section Chapter, SSC37 Part II Date: 16 Mar 2021 Time: 04:10 PM to 05:40 PM Location: Virtual Organizer(s): IEEE Toronto SSCS Contact: Toronto Section Chapter, SSC37 Speaker(s): Anthony Chan Carusone Biography: Prof. Tony Chan Carusone has taught and researched integrated circuits and systems at the University of Toronto since completing his Ph.D. there in 2002. He and his graduate students have received seven best-paper awards at leading conferences for their work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation. Prof. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and currently serves on the Technical Program Committee of the International Solid-State Circuits Conference. He has co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017 and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters.

  • Wideband Digital-to-Analog Converters for mmWave Transmitter

    Toronto, Ontario, Canada, Virtual: https://events.vtools.ieee.org/m/309574

    Over the past ten years, the data rate of cellular communication networks has increased by 100x. The next-generation software-defined-radio based wireless transmission in mmWave bands demands multi-GHz bandwidth digital-to-analog conversion with medium to high resolution (e.g., 14-16 bit) and sampling rates beyond 10GS/s. The rate of bandwidth increase and the required improvements in energy efficiency have exceeded the benefits of CMOS process scaling alone. There are compelling needs for novel architecture and circuit design techniques. In this talk, I will review recent development and present emerging parallel-path DAC architectures for extending the bandwidth with higher power and area efficiency than conventional interleaving designs. I will discuss the practical challenges along with several key analog design techniques. I will conclude with some future directions. At the end of the talk, I will briefly introduce some other research activities in my group, such as low power bioelectronics, neural interfacing and modulation circuits, and machine-learning accelerators. Speaker(s): Dr. Xilin Liu Virtual: https://events.vtools.ieee.org/m/309574 Biography: Dr. Xilin Liu (Senior Member, IEEE) is currently an Assistant Professor at the University of Toronto. He obtained his Ph.D. degree from the University of Pennsylvania. Before joining the University of Toronto in 2021, he held industrial positions at Qualcomm Inc., where he conducted R&D of high-performance mixed-signal circuits for cellular communication. He led and contributed to the IPs that have been integrated into products in high-volume production, including the industry’s first 5G chipset. He was a visiting scholar at Princeton University in 2014. He has co-authored two books along with over 30 peer-reviewed articles. He was the first author of the papers that have received the Best Student Paper Award at the 2017 ISCAS, the Best Paper Award at the 2015 BioCAS, the Best Track Award at the 2014 ISCAS, and the student research preview (SRP) award at 2014 ISSCC. He also received the SSCS predoctoral achievement award at the 2016 ISSCC.

  • IEEE EDS Distinguished Lecture: Low Power Design and Predictive Failure Analytics in Silicon in nm Era

    Room: BA2155, Bldg: Bahen Centre for Information Technology, 40 St George St , Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/331087

    Power has become the key driving force in processor as well AI specific accelerator designs as the frequency scale-up is reaching saturation. In order to achieve low power system, circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale VLSI circuits. Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates. This talk consists of pros and cons analysis on technology from power perspective and various techniques to exploit lower power. As the technology pushes towards sub-7nm era, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power, leakage power, short circuit power and collision power are covered. Usage of clock gating, power gating, longer channel, multi-Vt design, stacking, header-footer device techniques and other methods are described for logic and memory used for processors and AI. Finally the talk summarizes key challenges in achieving low power. In addition the tutorial gives a brief overview of predictive failure analytics used in nm Technology. Process and environmental variations impact circuit behavior it is important to model their effects to build robust circuits. The tutorial describe how key statistical techniques can be effectively used to analyze and build robust circuits. Speaker(s): Dr. Rajiv Joshi, Agenda: The event will start at 18:00PM EST and the talk will start at 18:10PM EST. Room: BA2155, Bldg: Bahen Centre for Information Technology, 40 St George St , Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/331087

  • SSCS Workshop: Pushing the Frontiers in Wireline Communication

    Room: SF1105, Bldg: Sanford Fleming Building, 10 King's College Road, University of Toronto, Toronto, Ontario, Canada, M5S 3G4

    Registration is free but required for this exciting in-person event. Detailed Agenda: 08:45 - 09:10 Coffee 09:10 - 09:15 Welcome Remarks: Dustin Dunwell, Toronto SSCS Chapter Vice-Chair 09:15 - 09:20 Opening Remarks: Ali Sheikholeslami, SSCS VP Education 09:20 - 10:20 Pushing the Energy Frontier in Wireline Communication - Davide Tonietto, Huawei Canada 10:20 - 10:40 Break 10:40 - 11:20 Pushing the Data Rates in Wireline Communication - Ali Sheikholeslami, University of Toronto, Canada 11:20 - 12:00 Error Propagation Detection and Correction in Wireline Communication - Hossein Shakiba, Huawei Canada 12:00 - 13:00 Lunch 13:00 - 13:40 Short Reach Interconnects for the Emerging Multi-Die System Era - Dino Toffolon, Synopys Canada 13:40 - 14:20 Interconnect IP: Past, Present, and into the Future - Robert Wang, Rambus Canada 14:20 - 14:40 Break 14:40 - 15:20 Trends in Wireline Communication - Kevin Parker, Marvell 15:20 - 16:00 Optimization Tools for Future Wireline Transceivers - Tony Chan Carusone, University of Toronto, Canada, and Alphawave 16:00 - 16:25 Panel Discussion, Moderated by Dustin Dunwell 16:25 - 16:30 Concluding Remarks, Dustin Dunwell Co-sponsored by: University of Toronto Room: SF1105, Bldg: Sanford Fleming Building, 10 King's College Road, University of Toronto, Toronto, Ontario, Canada, M5S 3G4

  • Distinguished Lecture Series: Wide Tuning-Range VCOs Using Multi-Mode Resonators

    Room: BA B025, Bldg: Bahen Centre for Information Technology, 40 St George St, Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/342962

    LC VCOs are commonly used for RF carrier generation. A wide tuning range in a single VCO is desirable for covering multiple bands while occupying a small area. An octave tuning range enables continuous coverage of all lower frequencies by integer frequency division. LC VCOs are most often tuned using variable capacitor banks and varactors. Because of switch resistances in capacitor banks and poor quality factor of varactors, using only capacitors for tuning degrades the phase noise, especially at millimeter-wave frequencies. Variable inductors using series switches pose the same problem. Mutual coupling can be exploited to realize multiple resonant modes with different effective inductances without using switches. This allows a wider tuning range without substantial reduction in the tank quality factor. Topologies for multi-mode resonant structures and their performance will be described with examples from the literature. Speaker(s): Dr. Krishnapura, Room: BA B025, Bldg: Bahen Centre for Information Technology, 40 St George St, Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/342962

  • IoT Workshop for Pre-University Educators (Kick-Off Meeting)

    Virtual: https://events.vtools.ieee.org/m/328095

    Network-based telemetry is embedded into virtually all modern products and systems in order to create new value for end users. Think of the Tesla automobile, that can update its own operating software, so the brakes work better! Pre-university ECE students need exposure to the hardware and protocols used in Internet-of-Things (“IoT”) enabled products, as well as the special challenges of designing these products. This 3-course, 12-week workshop will help you incorporate networking concepts and technology into your curriculum, and provide opportunities for your students to practice adding networking functionality to embedded projects. The courseware is based on a simple, network-enabled line-following robot based on the Raspberry Pi Pico W board, which will be provided to each participant. This training is targeted towards Grade 11/12 Computer or Electronics Engineering Teachers (Ontario TEJ/ICS Curriculum), and will be delivered virtually using a Learning Management System, combined with weekly live Q/A sessions to verify mastery of the material. When registering, please complete all address fields, so we can ship you a robot kit in time for the first session! To learn more about the courses that will be covered in this workshop, please visit the following page: https://www.cool-mcu.com/bundles/ieee-iot-workshop-for-pre-university-educators Agenda: Kick-Off Meeting Agenda: Outcomes Courses & Topic Coverage IoT Robot Hardware Review Using the LMS Detailed Training Schedule Assigned reading and lab exercise Virtual: https://events.vtools.ieee.org/m/328095

  • THE ROLE OF CO-PACKAGED OPTICS IN OUR CONNECTED FUTURE

    Room: GB119, Bldg: Galbraith Building, University of Toronto, Toronto, Ontario, Canada

    Progress in computation and communication is increasingly bottlenecked by integrated circuit I/0. CMOS technology scaling has enabled the integration of hundreds of complete modems operating over 100Gbps on a single chip. Whereas optical links were previously reserved for communication over 100's of kilometres, they are now the primary solution for chip-to-chip links above 100 Gbps over any distance beyond a few metres. Co-packaged optics (CPO) bring optics right to the perimeter of our electronic integrated circuits, and may therefore appear to be a natural continuation of this trend. Indeed, PO holds the promise of simultaneously lowering system power consumption, decreasing I/0 latency, and increasing the total bandwidth of chip I/O. And yet, at the same time, it has the potential to increase the power density, increase the cost, and limit the bandwidth density of our chio I/O. This talk will clarify these seeming contradictions, and paint a realistic picture of CPO's role in future connectivity. Co-sponsored by: SPIE OPTICA Student Chapter Speaker(s): Dr. Tony Chan Carusone, Room: GB119, Bldg: Galbraith Building, University of Toronto, Toronto, Ontario, Canada