Solid-State Circuits

Friday, August 10th 2018, the IEEE Toronto SSCS/CAS invites you to the IEEE SSCS/CAS Distinguished Lecture Series on: “A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC” by Lukang Shi and Gabor C. Temes, and “Noise Filtering and Linearization of Single-Ended Circuits” by Gabor C. Temes et al., School of EECS, Oregon State University. Date: Friday August 10th, 2018 Organizers: IEEE Toronto SSCS/CAS Location: Bahen Centre Room BA1210 Lecture 1 (10:10am – 11:00am): A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC Speakers: Lukang Shi and Gabor C. Temes School of EECS, Oregon State University Abstract: An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread in the DAC is much smaller than that of the conventional binary-weighted capacitor array, and the mismatch error can be greatly reduced. The circuit provides first-order noise shaping, which can improve the ADC’s linearity even for a small oversampling ratio. Also, the proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing noise mitigation schemes and higher-order noise shaping. These topics will also be discussed. Lecture 2 (11:10am – 12:00pm): Noise Filtering and Linearization of Single-Ended Circuits Speakers: Gabor C. Temes et al. School of EECS, Oregon State University Abstract: The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for suppressing the effects of the low-frequency noise. In this paper, existing techniques are described for noise mitigation. Also, a novel approach is proposed, which can suppress low-frequency noise. In addition, the new process will also reduce even-order distortion, another major limitation of analog circuits. Finally, it may allow the use of single-ended circuits in applications where usually differential structures are needed. Biography: Gabor C. Temes received the Ph.D. degree in electrical engineering from the University of Ottawa, ON, Canada, in 1961, and an honorary doctorate from the Technical University of Budapest, Budapest, Hungary, in 1991. He held academic positions at the Technical University of Budapest, Stanford University and the University of California at Los Angeles. He worked in industry at Northern Electric R&D Laboratories and at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science at Oregon State University. Dr. Temes received the IEEE Leon K. Kirchmayer Graduate Teaching Award in 1998, and the IEEE Millennium Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award, and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 Semiconductor Industry Association-SRC University Researcher Award. He is a member of the National Academy of Engineering.

Thursday Nov 15, 2018 at 1:30 p.m. Dr. Daniel Friedman, Distinguished Research Staff Member, IBM T.J. Watson Research Center, will be presenting “SSCS Distinguished Lecture: Considerations and Implementations For High Data Rate Interconnect”. Day & Time: Thursday November 15th, 2018 1:30 p.m. ‐ 2:30 p.m. Speaker: Dr. Daniel Friedman Distinguished Research Staff Member IBM T.J. Watson Research Center Organizers: IEEE Toronto Solid-State Circuits Society Location: Bahen Centre Room B024 40 St. George Street Toronto, ON M5S 2E4 Contact: Dustin Dunwell Abstract: Cloud computing requires many different interconnects. These links provide connectivity between and among CPUs, accelerators, memory, and switches; each link comes with its own distance and bandwidth requirements. Wireline transceivers are responsible for sending and receiving data from one chip to and from another, thus enabling required connectivity. Key specifications for such designs include data rate, power consumption, area, and connection distance. Distance and data rate specifications, in particular, drive the choice of physical channel to be used for the connection, which in turn drives requirements including the equalization capabilities of the transceiver. For short chip-to-chip channels with limited frequency-dependent loss, simple transceivers with little or no integrated equalization are appropriate, while for longer channels crossing backplanes and involving multiple transitions through connectors, complex transceivers with adaptive transmit and receive equalization are the right choice. As connection distances grow even longer, optical interconnect becomes an attractive option. In this talk, a framework for understanding serial link design will be presented, including a discussion of basic equalization strategies and key challenges. Next, several design examples will be presented, covering approaches to key classes of interconnect, from short reach channels to backplane channels to enabling highly integrated optical approaches. The talk will conclude with a discussion of emerging directions in this field. Biography: Daniel Friedman is currently a Distinguished Research Staff Member and Senior Manager of the Communication Circuits and Systems department of the IBM Thomas J. Watson Research Center. He received his doctorate from Harvard University in 1992 and subsequently completed post-doctoral work at Harvard and consulting work at MIT Lincoln labs, broadly in the area of image sensor design. After joining IBM in 1994, he initially developed field-powered RFID tags before turning to high data rate wireline and wireless communication. His current research interests include high-speed I/O design, PLL design, mmWave circuits and systems, and circuit/system approaches to enabling new computing paradigms. He was a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the 2009 JSSC Best Paper Award (given in 2011), and the 2017 ISSCC Lewis Winner Outstanding Paper Award; he holds more than 50 patents and has authored or co-authored more than 75 publications. He was a member of the BCTM technical program committee from 2003-2008 and of the ISSCC international technical program committee from ISSCC 2009 through ISSCC 2016; he served as the Wireline sub-committee chair from ISSCC 2012 through ISSCC 2016. He has served as the Short Course Chair from ISSCC 2017 to the present and is a member of the SSCS Adcom since 2018.

Thursday, November 22nd 2018, Vivienne Sze, Associate Professor at MIT in the Electrical Engineering and Computer Science Department, is presenting “Energy-Efficient Edge Computing for AI-driven Applications”. Day & Time: Thursday November 22nd, 2018 4:10 p.m. ‐ 5:00 p.m. Speaker: Vivienne Sze Associate Professor, MIT in the Electrical Engineering and Computer Science Department Organizers: IEEE Toronto Solid-State Circuits Society Location: Sanford Fleming Building, Room 1105 10 King’s College Rd Toronto, Ontario Canada M5S 3G4 Contact: Dustin Dunwell Abstract: Edge computing near the sensor is preferred over the cloud due to privacy and/or latency concerns for a wide range of applications including robotics/drones, self-driving cars, smart Internet of Things, and portable/wearable electronics. However, at the sensor there are often stringent constraints on energy consumption and cost in addition to throughput and accuracy requirements. In this talk, we will describe how joint algorithm and hardware design can be used to reduce energy consumption while delivering real-time and robust performance for applications including deep learning, computer vision, autonomous navigation and video/image processing. We will show how energy-efficient techniques that exploit correlation and sparsity to reduce compute, data movement and storage costs can be applied to various AI tasks including object detection, image classification, depth estimation, super-resolution, localization and mapping. Biography: Vivienne Sze is an Associate Professor at MIT in the Electrical Engineering and Computer Science Department. Her research interests include energy-aware signal processing algorithms, and low-power circuit and system design for portable multimedia applications, including computer vision, deep learning, autonomous navigation, and video process/coding. Prior to joining MIT, she was a Member of Technical Staff in the R&D Center at TI, where she designed low-power algorithms and architectures for video coding. She also represented TI in the JCT-VC committee of ITU-T and ISO/IEC standards body during the development of High Efficiency Video Coding (HEVC), which received a Primetime Emmy Engineering Award. She is a co-editor of the book entitled “High Efficiency Video Coding (HEVC): Algorithms and Architectures” (Springer, 2014). Prof. Sze received the B.A.Sc. degree from the University of Toronto in 2004, and the S.M. and Ph.D. degree from MIT in 2006 and 2010, respectively. In 2011, she received the Jin-Au Kong Outstanding Doctoral Thesis Prize in Electrical Engineering at MIT. She is a recipient of the 2018 Facebook Hardware & Software Systems Research Award, the 2017 Qualcomm Faculty Award, the 2016 Google Faculty Research Award, the 2016 AFOSR Young Investigator Research Program (YIP) Award, the 2016 3M Non-Tenured Faculty Award, the 2014 DARPA Young Faculty Award, the 2007 DAC/ISSCC Student Design Contest Award, and a co-recipient of the 2017 CICC Outstanding Invited Paper Award, the 2016 IEEE Micro Top Picks Award and the 2008 A-SSCC Outstanding Design Award. For more information about research in the Energy-Efficient Multimedia Systems Group at MIT visit: http://www.rle.mit.edu/eems/

Monday December 17th, 2018 at 1:10 p.m. Dr. Sorin Voinigescu, Professor at the University of Toronto, will be presenting a SSCS distinguished lecture: “The Qubit is the Transistor: Si-based Transistor and Analog-Mixed-Signal Circuit Scaling and the Natural Progression of Moore’s Law to Silicon Quantum Computing at the Atomic Scale”. Day & Time: Monday December 17th, 2018 1:10 p.m. ‐ 2:30 p.m. Speaker: Dr. Sorin Voinigescu Professor, University of Toronto Organizers: SSCS IEEE Toronto Location: Bahen Centre, Room BA1230 40 St George St, Toronto, ON M5S 2E4 Contact: Dustin Dunwell Abstract: Quantum computing is a hot topic at very cool temperatures. Cool as in 10-100 mK. Recently, a cold-atom physicist nonchalantly asked me the question: Why are you interested in high temperature quantum computers? High as in 4 -12 K. He was serious! Need I talk about Global Warming in such cool environments? Pluto is another option. Today, quantum computers consist of racks of microwave and analog-mixed-signal test equipment, FPGAs and feedback loops for error correction, long 50-Ohm coaxial cables, and a few qubits formed with non-linear Josephson-junction resonators, entangled through niobium superconducting λ/4 resonators at 8-20 GHz, biased by a DC magnetic field of up to 1 Tesla, and whose spin is controlled by an AC magnetic field rotating in the “lab frame”. Are you still spinning? There’s talk of electrons as “microwave photons”, Larmor and Rabi frequencies, photon-to-spin entanglement, RAP (as in rapid adiabatic passage), Bloch sphere, tensors in n-dimensional Hilbert spaces, but also of OFDM, phase noise, I-Q up- and down- conversion, Gaussian pulse modulation, coherent π/2, π/4 spin phase rotations in azimuth and elevation. Qubits are logic gates and memory cells at the same time. Logic gate operations consist of synchronized microwave pulses applied sequentially to the same qubits. The only probabilistic part (need I mention Schrodinger’s cats Flip and Flop?) is readout, when the spin state is projected on the Z (DC magnetic field) axis! In other words, quantum computing is about everything you learned and thought you’d never use again, should have learned, or you were never taught in undergrad and grad school in math, quantum and atomic physics, electronics, electromagnetics, and computer science… This talk will first attempt to demystify and translate the physics of quantum computing to an electronics engineer jargon. Next, I will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology, and explore their scalability through simulation to 2nm dimensions, when the coupling energy, ΔE, becomes comparable to thermal noise at 77-300 K. Silicon electron-spin and hole-spin coupled quantum-dot (QD) qubits have attracted a lot of interest recently due to their potential for integration in commercial CMOS technology. However, like their more established superconducting cousins, to date, because of the low confinement and coupling energies (e.g. ΔE, in the tens of μeV range, comparable to the thermal noise level, kBT, at 100 mK) their operation has been restricted to temperatures below 100 mK. Moreover, since cryogenic systems cannot remove more than a few μW of thermal power at 100 mK, and the experimental laboratory (think TNC at U of T versus TSMC 7nm fab) technologies in which these qubits have been realized do not allow for fabrication of spin manipulation and readout circuitry, the latter reside on a separate chip, at 4 K or higher temperature. The lack of monolithic integration further degrades readout fidelity and computing speed because the atto-Farad capacitance, high-impedance qubit needs to drive 50Ω and 100x larger capacitance interconnect off- chip. A qubit with higher confinement and coupling energies, with spin resonance in the upper mm-wave region, will allow for higher temperature operation, alleviating these problems and enabling large-scale monolithic quantum computing processors. For example, a qubit operating at 4 K would require mode splitting energies of 0.25 meV which corresponds to a spin resonance frequency of 60 GHz and require a DC magnetic field of 2.5 T. Simplifying a bit, 240GHz spin-resonance frequencies and 9T magnetic fields should be adequate for 12K operation and 1.4 THz with an humongous magnetic field are needed for 77 K. You get the drift… Finally, I will briefly review hot-off-the-press results obtained here at U of T. For the first time we report (i) integration of qubits and electronics on the same die, (ii) strained SiGe hole-spin and strained Si electron-spin FDSOI qubits on the same die, and (iii) propose a monolithic processor architecture which allows for short, 10-20ps spin control pulses and high Rabi frequencies, fRabi, to compensate for short spin phase coherence lifetime. We also demonstrate that, at 2 K, MOSFETs and cascodes can be operated as QDs in the subthreshold region while behaving as classical MOSFETs and cascodes in the saturation region, suitable for qubits and mm-wave mixed-signal processing circuits, respectively. If we still have holiday time left, I will go through a tutorial example of how we can derive the specification for the mm-wave spin manipulation and readout circuits starting from the Hamiltonian and the measured I-V characteristics of our SiGe hole-spin qubits. I may touch on the impact of minimum-size (18nmx6nmx80nm) MOSFET ofset voltage and process variation on qubit characteristics, on spin manipulation and readout architectural options (low phase-noise radar, OFDM radio, low-noise, broadband, ultra-high-gain TIAs), mm-wave switch impact and OFDM sub-carrier spacing on qubit crosstalk and isolation…Or maybe we should leave that for New Years’.

On Thursday, January 28, 2021 at 4:10 p.m., Ravi Shivnaraine will present give a talk, “A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS”. Day & Time: Thursday, January 28, 2021 4:10 p.m. – 5:00 p.m. Speaker(s): Ravi Shivnaraine of Rambus Organizer(s): IEEE Toronto Solid-State Circuits Society Location: Virtual – Zoom Contact: Saba Zargham Abstract: In this talk, Rambus will review their recent 26.5625Gbps to 106.25Gbps XSR SerDes macro in 7nm CMOS. The talk will go over the system architecture, self-test features, and measurement results. A 1.55pJ/b power efficiency and beachfront density of 722Gbps/mm have been achieved. Register: Please visit https://events.vtools.ieee.org/m/257895 to register and to view the Zoom link. Biography: Mr. Shivnaraine obtained his Bachelors and Masters from the University of Toronto in 2010 and 2012 respectively. Ravi has experience working on SerDes receivers at Snowbush, Huawei, and Rambus at 28Gbps, 56Gbps, and 112Gbps. Currently, he is at AnalogX working on next-generation SerDes in deep sub-micron nodes. His research interests are low power SerDes interfaces and digitally assisted analog techniques.

Recording: Click here to view Part I of the talk. The humble analog delay is simple in principle but complicated in practice. Analog delays are useful in analog filters, distributed amplifiers, and time-interleaved or pipelined analog signal processing. Unfortunately, it can be quite tricky to delay a continuous-time broadband analog waveform without distortion on an integrated circuit! Over the past two decades, our lab has repeatedly encountered the need for integrated broadband analog delays and has done much work on their implementation. Now that CMOS technologies can readily process analog signals with 10’s of GHz of bandwidth, analog delays less than one nanosecond are being used in new and creative ways. This talk reviews delay approximation and the implementation of delays from 10’s to 100’s of picoseconds having bandwidths up to 10’s of GHz. Case studies are presented using the analog delay circuits in FIR and IIR filters for wireline transceivers and in high-speed data converters. Part I Date: 10 Mar 2021 Time: 04:10 PM to 05:00 PM Location: Virtual Organizer(s): IEEE Toronto SSCS Contact: Toronto Section Chapter, SSC37 Part II Date: 16 Mar 2021 Time: 04:10 PM to 05:40 PM Location: Virtual Organizer(s): IEEE Toronto SSCS Contact: Toronto Section Chapter, SSC37 Speaker(s): Anthony Chan Carusone Biography: Prof. Tony Chan Carusone has taught and researched integrated circuits and systems at the University of Toronto since completing his Ph.D. there in 2002. He and his graduate students have received seven best-paper awards at leading conferences for their work on chip-to-chip and optical communication circuits, analog-to-digital conversion, and precise clock generation. Prof. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and currently serves on the Technical Program Committee of the International Solid-State Circuits Conference. He has co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017 and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters.

Over the past ten years, the data rate of cellular communication networks has increased by 100x. The next-generation software-defined-radio based wireless transmission in mmWave bands demands multi-GHz bandwidth digital-to-analog conversion with medium to high resolution (e.g., 14-16 bit) and sampling rates beyond 10GS/s. The rate of bandwidth increase and the required improvements in energy efficiency have exceeded the benefits of CMOS process scaling alone. There are compelling needs for novel architecture and circuit design techniques. In this talk, I will review recent development and present emerging parallel-path DAC architectures for extending the bandwidth with higher power and area efficiency than conventional interleaving designs. I will discuss the practical challenges along with several key analog design techniques. I will conclude with some future directions. At the end of the talk, I will briefly introduce some other research activities in my group, such as low power bioelectronics, neural interfacing and modulation circuits, and machine-learning accelerators. Speaker(s): Dr. Xilin Liu Virtual: https://events.vtools.ieee.org/m/309574 Biography: Dr. Xilin Liu (Senior Member, IEEE) is currently an Assistant Professor at the University of Toronto. He obtained his Ph.D. degree from the University of Pennsylvania. Before joining the University of Toronto in 2021, he held industrial positions at Qualcomm Inc., where he conducted R&D of high-performance mixed-signal circuits for cellular communication. He led and contributed to the IPs that have been integrated into products in high-volume production, including the industry’s first 5G chipset. He was a visiting scholar at Princeton University in 2014. He has co-authored two books along with over 30 peer-reviewed articles. He was the first author of the papers that have received the Best Student Paper Award at the 2017 ISCAS, the Best Paper Award at the 2015 BioCAS, the Best Track Award at the 2014 ISCAS, and the student research preview (SRP) award at 2014 ISSCC. He also received the SSCS predoctoral achievement award at the 2016 ISSCC.

Registration is free but required for this exciting in-person event. Detailed Agenda: 08:45 - 09:10 Coffee 09:10 - 09:15 Welcome Remarks: Dustin Dunwell, Toronto SSCS Chapter Vice-Chair 09:15 - 09:20 Opening Remarks: Ali Sheikholeslami, SSCS VP Education 09:20 - 10:20 Pushing the Energy Frontier in Wireline Communication - Davide Tonietto, Huawei Canada 10:20 - 10:40 Break 10:40 - 11:20 Pushing the Data Rates in Wireline Communication - Ali Sheikholeslami, University of Toronto, Canada 11:20 - 12:00 Error Propagation Detection and Correction in Wireline Communication - Hossein Shakiba, Huawei Canada 12:00 - 13:00 Lunch 13:00 - 13:40 Short Reach Interconnects for the Emerging Multi-Die System Era - Dino Toffolon, Synopys Canada 13:40 - 14:20 Interconnect IP: Past, Present, and into the Future - Robert Wang, Rambus Canada 14:20 - 14:40 Break 14:40 - 15:20 Trends in Wireline Communication - Kevin Parker, Marvell 15:20 - 16:00 Optimization Tools for Future Wireline Transceivers - Tony Chan Carusone, University of Toronto, Canada, and Alphawave 16:00 - 16:25 Panel Discussion, Moderated by Dustin Dunwell 16:25 - 16:30 Concluding Remarks, Dustin Dunwell Co-sponsored by: University of Toronto Room: SF1105, Bldg: Sanford Fleming Building, 10 King's College Road, University of Toronto, Toronto, Ontario, Canada, M5S 3G4

LC VCOs are commonly used for RF carrier generation. A wide tuning range in a single VCO is desirable for covering multiple bands while occupying a small area. An octave tuning range enables continuous coverage of all lower frequencies by integer frequency division. LC VCOs are most often tuned using variable capacitor banks and varactors. Because of switch resistances in capacitor banks and poor quality factor of varactors, using only capacitors for tuning degrades the phase noise, especially at millimeter-wave frequencies. Variable inductors using series switches pose the same problem. Mutual coupling can be exploited to realize multiple resonant modes with different effective inductances without using switches. This allows a wider tuning range without substantial reduction in the tank quality factor. Topologies for multi-mode resonant structures and their performance will be described with examples from the literature. Speaker(s): Dr. Krishnapura, Room: BA B025, Bldg: Bahen Centre for Information Technology, 40 St George St, Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/342962

Network-based telemetry is embedded into virtually all modern products and systems in order to create new value for end users. Think of the Tesla automobile, that can update its own operating software, so the brakes work better! Pre-university ECE students need exposure to the hardware and protocols used in Internet-of-Things (“IoT”) enabled products, as well as the special challenges of designing these products. This 3-course, 12-week workshop will help you incorporate networking concepts and technology into your curriculum, and provide opportunities for your students to practice adding networking functionality to embedded projects. The courseware is based on a simple, network-enabled line-following robot based on the Raspberry Pi Pico W board, which will be provided to each participant. This training is targeted towards Grade 11/12 Computer or Electronics Engineering Teachers (Ontario TEJ/ICS Curriculum), and will be delivered virtually using a Learning Management System, combined with weekly live Q/A sessions to verify mastery of the material. When registering, please complete all address fields, so we can ship you a robot kit in time for the first session! To learn more about the courses that will be covered in this workshop, please visit the following page: https://www.cool-mcu.com/bundles/ieee-iot-workshop-for-pre-university-educators Agenda: Kick-Off Meeting Agenda: Outcomes Courses & Topic Coverage IoT Robot Hardware Review Using the LMS Detailed Training Schedule Assigned reading and lab exercise Virtual: https://events.vtools.ieee.org/m/328095

Progress in computation and communication is increasingly bottlenecked by integrated circuit I/0. CMOS technology scaling has enabled the integration of hundreds of complete modems operating over 100Gbps on a single chip. Whereas optical links were previously reserved for communication over 100's of kilometres, they are now the primary solution for chip-to-chip links above 100 Gbps over any distance beyond a few metres. Co-packaged optics (CPO) bring optics right to the perimeter of our electronic integrated circuits, and may therefore appear to be a natural continuation of this trend. Indeed, PO holds the promise of simultaneously lowering system power consumption, decreasing I/0 latency, and increasing the total bandwidth of chip I/O. And yet, at the same time, it has the potential to increase the power density, increase the cost, and limit the bandwidth density of our chio I/O. This talk will clarify these seeming contradictions, and paint a realistic picture of CPO's role in future connectivity. Co-sponsored by: SPIE OPTICA Student Chapter Speaker(s): Dr. Tony Chan Carusone, Room: GB119, Bldg: Galbraith Building, University of Toronto, Toronto, Ontario, Canada