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  • Career Night Series: Writing Attention Grabbing Resumes

    On Tuesday, January 19, 2021 at 6:00 p.m., IEEE Toronto WIE and IM/RA will host “Career Night Series: Writing Attention Grabbing Resumes & Cover Letters”. Day & Time: Tuesday, January 19, 2021 9:00 p.m. – 10:30 p.m. Organizers: IEEE Toronto WIE, IM/RA, Ryerson Computer Science Location: Virtual Contact: Wincy Li Description: Unclear about how to tailor a resume to industry jobs? Want to learn how to describe your accomplishments in an impactful manner? In this webinar, you will learn how to gain the attention of hiring managers with well-written resumes and cover letters! For accessibility needs, please contact Wincy at wincyli@ryerson.ca as soon as possible. Register: Please visit https://ryerson.zoom.us/webinar/register/WN_K0eDFX2LQtu97tfq0Wpy_w to register.

  • JOINT EPS/CAS WEBINAR: FLEXIBLE HYBRID ELECTRONICS 2.0

    On Thursday, January 21, 2021 at 9:00 p.m., the IEEE Toronto Circuits & Devices Chapter invites you to attend a Distinguished Lecture webinar co-sponsored by the IEEE OREGON JOINT EPS/CAS CHAPTER. Day & Time: Thursday, January 21, 2021 9:00 p.m. – 10:30 p.m. Speaker: Subramanian Iyer of UCLA Organizer(s): IEEE Toronto Circuits & Devices Chapter, IEEE Oregon Joint EPS/CAS Chapter Location: Virtual (Webex) Connect info sent to registered attendees Contact: Mengqi Wang, James Morris Abstract: In the last few years, electronics packaging has rightfully emerged from the shadows of CMOS scaling to make a significant impact in high performance and mobile appliance computing. The area of Flexible Hybrid Electronics (FHE) has also developed and is making a significant impact in the area of medical and wellness electronics. The first generation of these devices have, for most part, adapted Printed Circuit Board (PCB) technology by using thinner PCBs and assembling either thinned or thin packaged “older” generation of chips on to these platforms, typically with coarse printed wiring to connect a small number of such chips. This approach, while immensely useful to get the field going, needs to adapt and borrow from the both silicon and advanced packaging technology trends, so that we can advance this trend to the next level. The key paradigm challenges ahead are: scaling the FHE in general – this includes the adoption of dielet (chiplet) technology in more advanced CMOS nodes including edge-AI, higher performance interconnects, flexible high-density energy storage, wireless communication and advanced ergonomics and all of these at lower cost and higher reliability. In this talk we will address these challenges and outline a possible technology roadmap to achieve these goals in the next few years. Register: Please visit https://events.vtools.ieee.org/m/256124 to register. Biography: Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and device innovations that they may enable wafer-scale architectures, in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 75 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors and iMAPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award. List of publications/patents: https://scholar.google.com/citations?user=xXV4oIMAAAAJ&hl=en Email: S.S.Iyer@ucla.edu

  • A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS

    On Thursday, January 28, 2021 at 4:10 p.m., Ravi Shivnaraine will present give a talk, “A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS”. Day & Time: Thursday, January 28, 2021 4:10 p.m. – 5:00 p.m. Speaker(s): Ravi Shivnaraine of Rambus Organizer(s): IEEE Toronto Solid-State Circuits Society Location: Virtual – Zoom Contact: Saba Zargham Abstract: In this talk, Rambus will review their recent 26.5625Gbps to 106.25Gbps XSR SerDes macro in 7nm CMOS. The talk will go over the system architecture, self-test features, and measurement results. A 1.55pJ/b power efficiency and beachfront density of 722Gbps/mm have been achieved. Register: Please visit https://events.vtools.ieee.org/m/257895 to register and to view the Zoom link. Biography: Mr. Shivnaraine obtained his Bachelors and Masters from the University of Toronto in 2010 and 2012 respectively. Ravi has experience working on SerDes receivers at Snowbush, Huawei, and Rambus at 28Gbps, 56Gbps, and 112Gbps. Currently, he is at AnalogX working on next-generation SerDes in deep sub-micron nodes. His research interests are low power SerDes interfaces and digitally assisted analog techniques.

  • IndustrioTech© Seminars – Smart Maintenance

    IEEE Toronto WIE and IM/RA is hosting “IndustrioTech”, a series of seminars on Smart Maintenance (Predictive Maintenance) using variety of technologies. Day & Time: Thursday, January 28, 2021 6:00 p.m. – 8:00 p.m. Speakers & Topics: Dr. Ahmad Barari Director of Advanced Digital Manufacturing and Advanced Digital Metrology Laboratories, Associate Professor at University of Ontario Institute of Technology Topic: LIVE Simulation for Predictive Maintenance Mohsen Tayefeh Industry 4.0 strategic Business manager, CAD MicroSolutions Topic: Imperative foundations toward Smart Maintenace: Matching up the Technology with the Business Value Shafiul Alam Research Engineer McMaster Manufacturing Research Institute (MMRI) Topic: Predictive Maintenance and Industry 4.0 (Case study Honda manufacturing plant) Dr. Amir Harandi CEO, Artintech Inc. Topic: ML and GA: Artificial Intelligent techniques in Smart Maintenance Organizer(s): IEEE Toronto WIE, IM/RA Location: Virtual Contact: Ayda Naserialiabadi Register: Please visit here to register.

  • Project-based Python Workshop 3

    On Friday, February 5, 2021 at 10:00 a.m., IEEE Toronto WIE will host a Python workshop, “How to Use LSTM for Text and Time Series Classification”. Day & Time: Friday, February 5, 2021 10:00 a.m. – 12:00 p.m. Speaker(s): Enas Tarawneh Organizer(s): IEEE Toronto WIE, York University WiCSE Location: Virtual Contact: Hina Tabassum Abstract: This workshop focuses on how to classify or label text using bi-LSTM RNNs. It includes pre-processing/cleaning of the text and handling severely imbalanced classes using SMOTE, oversampling, under-sampling, class count, and log smoothen weights. Using different types of LSTM such as vanilla LSTM, and Bi-LSTM, we focus on time series problems with categorical data.  In summary, this workshop will cover: a) Preprocessing text and data b) Handling imbalanced datasets c) Use different types of LSTMs for text and time series classification d) Produce meaningful classification reports Register: Please visit http://bit.ly/39IQFXd to register. Biography: Enas Tarawneh is a PhD student at York University in the department of Computer Science and Electrical Engineering. She works in the Vision, Graphics and Robotics (VGR) Laboratory as a research assistant. Her most recent research involves the development and evaluation of a cloud-based avatar (intelligent agent) for human-robot interaction that is part of a project funded by VISTA. She holds an OGS and VISTA doctoral scholarship.  Prior to this, Enas worked as an academic Lead, instructor, and e-learning coordinator in the Institute of Applied Technology in UAE in which she received an award for “Distinguished Curriculum Support” and another for “Excellence in E-learning coordination”. Most importantly, Enas is a wife and mother of three, that believes that open-mindedness and positivism is the best accomplishment and the source of true happiness.

  • Glide symmetries: a new degree of freedom for the design of periodic structures

    Toronto, Ontario Canada

    On Monday, February 8, 2021 at 11:00 a.m., IEEE Antennas and Propagation Society is hosting “Glide Symmetries: A New Degree of Freedom for the Design of Periodic Structures”. Day & Time: Monday, February 8, 2021 11:00 a.m. – 12:30 p.m. Speaker: Oscar Quevedo-Teruel of KTH Royal Institute of Technology Organizer(s): IEEE Antennas and Propagation Society Location: Virtual – Zoom Contact: George Eleftheriades Abstract: Glide symmetries were employed for electromagnetic purposes during the 60s and 70s. Those works were focused on one-dimensional structures with potential application in low-dispersive leaky wave antennas. However, the development of planar/printed technologies in the 80s and 90s associated to their low-cost for low-frequency applications, the studies of glide symmetries stopped. In the beginning of the 21st century, with arrival of metamaterials, there was a significant development of the understanding of periodic structures, and new methods of analysis were introduced. This theoretical development, together with the interest of industry in mm-waves, particularly for communications systems such as 5G, created an opportunity to explore the possibilities of glide symmetries, especially in two-dimensional configurations. Glide-symmetric structures has recently attracted the attention of researchers due to their attractive properties for practical applications. Among their interesting properties are low-dispersive responses in fully metallic structures such as parallel plate or co-planar waveguides (CPW), bandgaps associated to the symmetries and large electromagnetic bandgaps (EBGs). In this talk, Dr. Quevedo-Teruel will describe the most significant works in glide symmetries, including their application for the design of gap-waveguide technology and planar lens antennas with steerable angles of radiation. Register: Please visit https://events.vtools.ieee.org/m/256420 to register. Biography: Oscar Quevedo-Teruel is a Senior Member of the IEEE. He received his Telecommunication Engineering Degree from Carlos III University of Madrid, Spain in 2005, part of which was done at Chalmers University of Technology in Gothenburg, Sweden. He obtained his Ph.D. from Carlos III University of Madrid in 2010 and was then invited as a postdoctoral researcher to the University of Delft (The Netherlands). From 2010-2011, Dr. Quevedo-Teruel joined the Department of Theoretical Physics of Condensed Matter at Universidad Autonoma de Madrid as a research fellow and went on to continue his postdoctoral research at Queen Mary University of London from 2011-2013. In 2014, he joined the Division for Electromagnetic Engineering in the School of Electrical Engineering and Computer Science at KTH Royal Institute of Technology in Stockholm, Sweden where he is an Associate Professor and Director of the Master Programme in Electromagnetics Fusion and Space Engineering. He has been an Associate Editor of the IEEE Transactions on Antennas and Propagation since 2018 and is the founder and editor-in-chief of the EurAAP journal Reviews of Electromagnetics. He was the EurAAP delegate for Sweden, Norway, and Iceland from 2018-2020 and he is now a member of the EurAAP Board of Directors. He is a distinguished lecturer of the IEEE Antennas and Propagation Society for the period of 2019-2022, and Chair of the IEEE APS Educational Initiatives Programme since 2020. He has made scientific contributions to higher symmetries, transformation optics, lens antennas, metasurfaces, leaky wave antennas, and high impedance surfaces. He is the co-author of 95 journal papers and 150 at international conferences.

  • Design And Analysis Of Chiplet Interfaces For Heterogeneous Systems

    On Thursday, February 11, 2021 at 2:50 p.m., Wendem Tsegaye Beyene will present the talk “Design And Analysis Of Chiplet Interfaces For Heterogeneous Systems”. Day & Time: Thursday, February 11, 2021 2:50 p.m. – 3:50 p.m. Speaker: Wendem Tsegaye Beyene Organizer(s): IEEE Silicon Valley/SF Bay Area Electronics Packaging Chapter Location: Virtual – Directions for connecting with the WebEx stream will be sent via email to all registrants 1-2 days prior to the event. Contact: Durand Jarrett-Amor, Annette Teng Abstract: The chiplet interface allows multiple silicon dies of various technologies and complexities to communicate efficiently using larger parallel interconnects in a single package. The second layer of interconnect on the package (silicon or organic interposer) provides dense channels as well as low impedance power delivery paths between multiple independent power domains. Although the channels are very short and the I/O power can be reduced by an order of magnitude, the huge increase in the transient current in multiple dies and the unique clocking architecture makes the supply noise and timing jitter the limiting factors in designing high-performance multi-die systems. This talk discusses the unique signal and power integrity challenges of chiplet interfaces. Register: Please visit https://eps2102.eventbrite.com to register for this event. Biography: Wendem Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign. In the past, he was employed by IBM, Hewlett-Packard, Agilent Technologies and Rambus Inc. He also worked as a principal Engineer with Intel Corp. managing a team working on modeling and analysis of power-delivery and signaling systems of digital-core and mixed-signal I/O subsystems of FPGA chips. He is an elected Associate Fellow of the Ethiopian Academy of Sciences, and has been selected as a Distinguished Llecturer for IEEE EPS as well as for IEEE EMCS Society.

  • Derivative Data Security using Artificial Intelligence

    Recorded Material: Please click here to view the recorded technical talk. On Thursday, February 18, 2021 at 6:00 p.m., IEEE Computer Chapter is hosting the technical talk “Derivative Data Security using Artificial Intelligence”. Day & Time: Thursday, February 18, 2021 6:00 p.m. – 9:00 p.m. Speaker: Zia Babar Organizer: IEEE Toronto Computer Chapter Location: Since this will be a virtual event we will relay the connectivity information later to individual registrants on their email addresses. Contact: Younas Abbas Abstract: Data security the most dynamic and ever evolving trade becomes even significant while dealing with large volumes of unstructured data. To comply with regulation and standards like GDPR it is important to understand, equip and keep abreast of new tools and techniques in data security. Enterprises are increasingly storing large volumes of unstructured data. However, irrespective of the data format or type, unstructured data is difficult to secure and control its transfer. This is a major problem due to evolving compliance policies and the need to adhere to standards such as GDPR. Through derivative data security practices, enterprises can utilize machine learning and deep learning techniques to determine and trace clones and derivatives of unstructured data across the enterprise. In this talk, Zia Babar will provide a background on data security approaches, and provide a demonstration on machine learning and deep learning techniques can be used for providing derivative data security. Register: Please visit https://events.vtools.ieee.org/m/252704 to register. Biography: Zia Babar (https://www.linkedin.com/in/zbabar/) has 20 years of professional industry experience, He has deep expertise in the design, development and deployment of enterprise applications, data engineering platforms and distributed systems, with a particular focus on incorporating machine learning practices and cognitive services into software applications. Zia obtained his PhD from the University of Toronto where his research studies focused on the analysis and design of cognitive systems for enabling enterprise transformation. He is presently the Director of Research and Development at WinMagic. Previously, he worked in companies like Teradata where he developed Teradata’s first ML framework, NCR where he was responsible for designing and developing large-scale data processing systems, and Luminous Networks (acquired by Cisco) where he designed and built distributed systems. He is also presently engaged in a multi-year research engagement with IBM Research Labs and is a startup technical mentor at WeWork Labs. Further, he is the organizer of multiple technology meetup groups in both Toronto and Waterloo, and a frequent speaker at technical events and conferences.

  • Isola High Speed Materials and Copper Foil Selection

    Kitchener, Ontario Canada

    On Tuesday, February 23, 2021 at 1:30 p.m., Michael J. Gay from Isola will present the technical presentation “Isola High Speed Materials and Copper Foil Selection“. Day & Time: Tuesday, February 23, 2021| 1:30 p.m. – 2:30 p.m. Speaker: Michael J. Gay Organizer(s): IEEE KW EMC/MAG joint Chapter, University of Toronto AP Student Chapter Location: Virtual – WebEx Contact: Ming Chang Wang, Parinaz Naseri Abstract: Are you running 10Gbps+ signal channel in your system? What PCB materials are suitable for 10Gbps+ application? How copper layer surface roughness affecting Signal Integrity, RF, etc? IEEE KW EMC/MAG joint Chapter and University of Toronto AP Student Chapter invite you to join this technical presentation of “Isola High Speed Materials and Copper Foil Selection” by Michael J. Gay from Isola. This event will be recorded for Asia Region attendees. Please register even you are not able to join live, so that you will be provided for a link with the recorded version later. Agenda: SI (Signal Integrity) Performance – Laminate versus SITV (Signal Integrity Test Vehicle) testing Tech road map Comparing Isola HSD product options Copper foil performance factors Isola Product Stack Isola foil testing method and results Register: Please visit https://events.vtools.ieee.org/m/260528 to register. Biography: Michael J. Gay currently holds the position of Director, High Performance Products with Isola. Michael has been with Isola for 20 years and has 25 years of experience in laminate and PCB manufacturing industries. He has held various positions at Isola which include Technical Sales Manager and Director Emerging Products Asia Pacific Region where his responsibilities ranged from new product introduction, PCB process development and technical support and troubleshooting for Isola customers. Since returning from his role in Asia, he has worked closely with major industry OEM’s to develop and qualify Isola materials for the next generation of technology. Michael is also active in various PCB industry organizations where he currently provides technical expertise to industry critical committees and projects. He received his Bachelor of Science in Mechanical Engineering and Masters of Business Administration from Portland State University.

  • CAS Distinguished Lecture – Circuit Design and Silicon Prototypes for Compute-in-Memory for Deep Learning Inference Engine

    Toronto, Ontario Canada

    Date & Time: March 4, 2021 2:00 P.M. – 3:00 P.M. Speaker(s): Dr. Shimeng Yu Location: Virtual Contact: Wagih Ismail Abstract: Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in the deep learning inference engine. SRAM and resistive random access memory (RRAM) are identified as two promising embedded memories to store the weights of the deep neural network (DNN) models. In this seminar, first I will review the recent progresses of SRAM and RRAM-CIM macros that are integrated with peripheral analog-to-digital converter (ADC). The bit cell variants (e.g. 6T SRAM, 8T SRAM, 1T1R, 2T2R) and array architectures that allow parallel weighted sum are discussed. State-of-the-art silicon prototypes are surveyed with normalized metrics such as energy efficiency (TOPS/W). Second, we will discuss the array-level characterizations of non-ideal device characteristics of RRAM, e.g. the variability and reliability of multilevel states, which may negatively affect the inference accuracy. Third, I will discuss the general challenges in CIM chip design with regards to the imperfect device properties, ADC overhead, and chip to chip variations. Finally, I will discuss future research directions including monolithic 3D integration of memory tier on top of the peripheral logic tier. Biography: Shimeng Yu is currently an associate professor of electrical and computer engineering at Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University. Prof. Yu’s research interests are the semiconductor devices and integrated circuits for energy-efficient computing systems. His research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator, in-memory computing, 3D integration, and hardware security. Among Prof. Yu’s honors, he was a recipient of NSF Faculty Early CAREER Award in 2016, IEEE Electron Devices Society (EDS) Early Career Award in 2017, ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020, and IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2021-2022, etc. Prof. Yu served or is serving many premier conferences as technical program committee, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology, IEEE International Reliability Physics Symposium (IRPS), ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE International Conference on Computer-Aided-Design (ICCAD), etc. He is a senior member of the IEEE. Email: shimeng.yu@ece.gatech.edu

  • Classifying Holes, Voids, Negative Objects and Nothing and Quantum Computing

    Date: Tuesday, March 9, 2021 Time: 1:00 p.m. - 2:00 p.m. Speakers: Katrina Hooper, Javaid Iqbal Zahid Location: Virtual - Zoom Organizers: IEEE Toronto WIE Contact: Maryam Davoudpour Abstracts: In the fields of Urban Search and Rescue (USAR), Search and Rescue (SAR) and autonomous travel, understanding the entirety of the environment is an asset and most times a requirement. For example, in USAR, it is in the spaces between objects within a rubble pile, which are a type of negative objects, where trapped people can be found and where structural instabilities are located. While most research focuses on classifying positive objects, we work to build a framework to understand negative objects and a set of standardized terminology to discuss and classify them. This presentation will discuss the necessity for creating a lexicon for negative objects, exhibit applications of negative object research, and suggest a starting point for vocabulary to reduce ambiguity around classes of negative objects. Furthermore, we aim to spark a discussion about negative object research and suggest a starting point for a novel research area. Quantum computing is one of the emerging technologies for the future. Quantum computing is based on the principles of quantum mechanics and fuses beautifully with computer science. It is often in the news when computing supremacy is discussed. Governments and big technology companies like, IBM, Google, Microsoft, Intel, etc. along with private partners, are heavily investing in this technology. Quantum mechanics is based on counterintuitive properties like superposition, entanglement, and interference that make it different from classical computing. It is expected to outperform classical computing in certain areas of applications, like medical science, computer science, and cryptography, to name a few. In this talk, we will discuss the fundamentals of quantum computing with an introduction to the principle/properties of quantum mechanics, its usefulness for representing information, and what operations can be performed on the information represented by Qubits. While quantum gates, the fundamental information processing units of quantum computing are based on mathematical constructs from Linear Algebra and Probability, classical computing is based on Boolean Algebra and Logics gates. A number of possibilities for representing and processing quantum information are much larger than classical computing – hence the promise of larger computer power of quantum computing. Biographies: Katrina Hooper Katrina is in her final year in her Computer Science Masters at Ryerson University. She holds an Honors BSc. from the University of Toronto with a specialist in Physics and a minor in Mathematics. Her interests are in the development of negative object research and imitation learning for chess engines. Under the supervision of Dr. Alex Ferworn, she works to build a lexicon and a classifier for negative objects. Javaid Iqbal Zahid Mr. Javaid Iqbal Zahid is currently a PhD student in Department of Computer Science, Ryerson University, and is supervised by Dr. Alex Ferworn. Mr. Javaid holds Bachelor of Science degree in Telecommunication Engineering and Master of Science degree in Electrical Engineering, specializing in Communications and Computing. Additionally, he obtained advanced training in Cryptology and Wireless communications. Inspired by Dr. Claude E. Shannon, he has special interest in information theory, cryptography. He has been involved in deployment and operations of data networks and datacenters for a large government organization. He has also been acting as chief information security officer (CISO). At Ryerson, he is currently conducting research in quantum computing with special attention in quantum cryptography. He is member of IEEE Computer, Communication, and Information Theory Societies.

  • In celebration of International Women’s Day Wearables in Healthcare: A Woman’s Perspective

    Join us for an afternoon celebrating the work of women in wearable technology focused on health and life stages. Network with women using and integrating tech for the value it can provide. Collaborate in workshops where we will co-design the future wearables, apps and services that address our priorities and needs. Date: 10 Mar 2021 Time: 03:00 PM to 05:00 PM Speaker(s): Renn Scott, Samira Rahimi Location: Virtual Organizer(s): IEEE Toronto WIE, IM/RA Contact: Toronto Section Affinity Group,WIE, Toronto Section Jt. Chapter, IM09/RA24 Biographies: Renn Scott; MA, Interaction Design, RCA, Founder + Chief Designer of Daily Goods Design LABS, Senior Director of UX + ID at Myant A design leader and prolific inventor, Renn has a passion for creating innovative user experiences and forward-thinking product designs. With over 20 years of experience at companies such as Myant, IBM and BlackBerry in leadership roles within user experience, design research, consumer insights and strategic innovation, Renn has helped design best in class products and experiences. Renn’s hands-on approach and point of view as a designer is radically different than most. For any project she always starts with ‘WHY create’ in the first place and uses a co-creative design methodology and best practices based on insights gained from female consumers. Renn’s experience and observations has been that there is a lack of female design leaders and designers in the tech and design fields. Instead of just leading by example Renn also strives to empower other women to make, create and innovate in the field of design, technology and fashion by sharing her insights, skills and knowledge through Daily Goods Design LABS pop ups and educational event series. Samira Rahimi Eng. Ph.D., Assistant Professor, Department of Family Medicine, McGill University Samira Rahimi Eng. Ph.D. is an Assistant Professor in the Department of Family Medicine at McGill University, affiliated scientist at Lady Davis Institute for Medical Research of the Jewish General Hospital, and academic member of Mila—Quebec AI Institute. She is FRQS Junior 1 Research Scholar in human-centered AI in primary health care. Her work as Principal Investigator has been funded by the Fonds de recherche du Québec – Santé (FRQS), Natural Sciences and Engineering Research Council (NSERC), Roche Canada, Brocher Foundation (Switzerland), and the Strategy for Patient-Oriented Research (SPOR)-Canadian Institutes of Health Research (CIHR). With an interdisciplinary background, Dr. Rahimi is interested in the development and implementation of clinical decision support tools and patient decision aids, as well as integrating human-centered AI tools in primary health care. She specializes in computational intelligence, decision making, and applied operational research in health care.