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GDSfactory, an Open Source flow for photonics & analog circuit design, verification and validation

Virtual: https://events.vtools.ieee.org/m/348254

For efficient design, verification and validation of integrated circuits and components it is important to have an easy to customize workflow. Python has become the standard programming language for machine learning, scientific computing and engineering. In this talk we describe the gdsfactory design automation tool. GDSfactory provides you an end to end workflow that combines layout, verification and validation, which is an extensible, open source, python driven flow for turning your chip designs into validated products. Speaker(s): Joaquin Matres, Ph.D., Virtual: https://events.vtools.ieee.org/m/348254

IEEE EPS Distinguished Lecture: Chiplet Design and Heterogeneous Integration Packaging

Bldg: Bahen Centre for Information Technology, 40 St George St, Room BA1240, Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/335514

[] Please note that this lecture has unfortunately had to be cancelled. Lecture notes from the talk will be shared with registrants. We sincerely apologize for the inconvenience. The IEEE Toronto Electronics Packaging Society is proud to present Distinguished Lecturer Dr. John Lau of Unimicron Technology Corporation and his talk on "Chiplet Design and Heterogeneous Integration Packaging". Abstract Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (either side-by-side, stacked, or both) with different sizes and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem on a common package substrate. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in chiplet design and heterogeneous integrationpackaging will be presented. Please join us Tuesday, December 13th at 11 AM in BA1240. The event will also be streamed live on Zoom for those who cannot attend in person. Food and refreshments will be served. Speaker(s): Dr. John H Lau, Bldg: Bahen Centre for Information Technology, 40 St George St, Room BA1240, Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/335514

IEEE EDS Distinguished Lecture: Low Power Design and Predictive Failure Analytics in Silicon in nm Era

Room: BA2155, Bldg: Bahen Centre for Information Technology, 40 St George St , Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/331087

Power has become the key driving force in processor as well AI specific accelerator designs as the frequency scale-up is reaching saturation. In order to achieve low power system, circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale VLSI circuits. Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates. This talk consists of pros and cons analysis on technology from power perspective and various techniques to exploit lower power. As the technology pushes towards sub-7nm era, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power, leakage power, short circuit power and collision power are covered. Usage of clock gating, power gating, longer channel, multi-Vt design, stacking, header-footer device techniques and other methods are described for logic and memory used for processors and AI. Finally the talk summarizes key challenges in achieving low power. In addition the tutorial gives a brief overview of predictive failure analytics used in nm Technology. Process and environmental variations impact circuit behavior it is important to model their effects to build robust circuits. The tutorial describe how key statistical techniques can be effectively used to analyze and build robust circuits. Speaker(s): Dr. Rajiv Joshi, Agenda: The event will start at 18:00PM EST and the talk will start at 18:10PM EST. Room: BA2155, Bldg: Bahen Centre for Information Technology, 40 St George St , Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/331087