Circuits & Devices

On Thursday, January 21, 2021 at 9:00 p.m., the IEEE Toronto Circuits & Devices Chapter invites you to attend a Distinguished Lecture webinar co-sponsored by the IEEE OREGON JOINT EPS/CAS CHAPTER. Day & Time: Thursday, January 21, 2021 9:00 p.m. – 10:30 p.m. Speaker: Subramanian Iyer of UCLA Organizer(s): IEEE Toronto Circuits & Devices Chapter, IEEE Oregon Joint EPS/CAS Chapter Location: Virtual (Webex) Connect info sent to registered attendees Contact: Mengqi Wang, James Morris Abstract: In the last few years, electronics packaging has rightfully emerged from the shadows of CMOS scaling to make a significant impact in high performance and mobile appliance computing. The area of Flexible Hybrid Electronics (FHE) has also developed and is making a significant impact in the area of medical and wellness electronics. The first generation of these devices have, for most part, adapted Printed Circuit Board (PCB) technology by using thinner PCBs and assembling either thinned or thin packaged “older” generation of chips on to these platforms, typically with coarse printed wiring to connect a small number of such chips. This approach, while immensely useful to get the field going, needs to adapt and borrow from the both silicon and advanced packaging technology trends, so that we can advance this trend to the next level. The key paradigm challenges ahead are: scaling the FHE in general – this includes the adoption of dielet (chiplet) technology in more advanced CMOS nodes including edge-AI, higher performance interconnects, flexible high-density energy storage, wireless communication and advanced ergonomics and all of these at lower cost and higher reliability. In this talk we will address these challenges and outline a possible technology roadmap to achieve these goals in the next few years. Register: Please visit https://events.vtools.ieee.org/m/256124 to register. Biography: Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and device innovations that they may enable wafer-scale architectures, in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 75 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors and iMAPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award. List of publications/patents: https://scholar.google.com/citations?user=xXV4oIMAAAAJ&hl=en Email: S.S.Iyer@ucla.edu

On Thursday, February 11, 2021 at 2:50 p.m., Wendem Tsegaye Beyene will present the talk “Design And Analysis Of Chiplet Interfaces For Heterogeneous Systems”. Day & Time: Thursday, February 11, 2021 2:50 p.m. – 3:50 p.m. Speaker: Wendem Tsegaye Beyene Organizer(s): IEEE Silicon Valley/SF Bay Area Electronics Packaging Chapter Location: Virtual – Directions for connecting with the WebEx stream will be sent via email to all registrants 1-2 days prior to the event. Contact: Durand Jarrett-Amor, Annette Teng Abstract: The chiplet interface allows multiple silicon dies of various technologies and complexities to communicate efficiently using larger parallel interconnects in a single package. The second layer of interconnect on the package (silicon or organic interposer) provides dense channels as well as low impedance power delivery paths between multiple independent power domains. Although the channels are very short and the I/O power can be reduced by an order of magnitude, the huge increase in the transient current in multiple dies and the unique clocking architecture makes the supply noise and timing jitter the limiting factors in designing high-performance multi-die systems. This talk discusses the unique signal and power integrity challenges of chiplet interfaces. Register: Please visit https://eps2102.eventbrite.com to register for this event. Biography: Wendem Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign. In the past, he was employed by IBM, Hewlett-Packard, Agilent Technologies and Rambus Inc. He also worked as a principal Engineer with Intel Corp. managing a team working on modeling and analysis of power-delivery and signaling systems of digital-core and mixed-signal I/O subsystems of FPGA chips. He is an elected Associate Fellow of the Ethiopian Academy of Sciences, and has been selected as a Distinguished Llecturer for IEEE EPS as well as for IEEE EMCS Society.

Date & Time: March 4, 2021 2:00 P.M. – 3:00 P.M. Speaker(s): Dr. Shimeng Yu Location: Virtual Contact: Wagih Ismail Abstract: Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in the deep learning inference engine. SRAM and resistive random access memory (RRAM) are identified as two promising embedded memories to store the weights of the deep neural network (DNN) models. In this seminar, first I will review the recent progresses of SRAM and RRAM-CIM macros that are integrated with peripheral analog-to-digital converter (ADC). The bit cell variants (e.g. 6T SRAM, 8T SRAM, 1T1R, 2T2R) and array architectures that allow parallel weighted sum are discussed. State-of-the-art silicon prototypes are surveyed with normalized metrics such as energy efficiency (TOPS/W). Second, we will discuss the array-level characterizations of non-ideal device characteristics of RRAM, e.g. the variability and reliability of multilevel states, which may negatively affect the inference accuracy. Third, I will discuss the general challenges in CIM chip design with regards to the imperfect device properties, ADC overhead, and chip to chip variations. Finally, I will discuss future research directions including monolithic 3D integration of memory tier on top of the peripheral logic tier. Biography: Shimeng Yu is currently an associate professor of electrical and computer engineering at Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University. Prof. Yu’s research interests are the semiconductor devices and integrated circuits for energy-efficient computing systems. His research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator, in-memory computing, 3D integration, and hardware security. Among Prof. Yu’s honors, he was a recipient of NSF Faculty Early CAREER Award in 2016, IEEE Electron Devices Society (EDS) Early Career Award in 2017, ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020, and IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2021-2022, etc. Prof. Yu served or is serving many premier conferences as technical program committee, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology, IEEE International Reliability Physics Symposium (IRPS), ACM/IEEE Design Automation Conference (DAC), ACM/IEEE Design, Automation & Test in Europe (DATE), ACM/IEEE International Conference on Computer-Aided-Design (ICCAD), etc. He is a senior member of the IEEE. Email: shimeng.yu@ece.gatech.edu

The Circuits & Devices Chapter of IEEE Toronto is pleased to invite you to join us for a virtual talk by Distinguished Lecturer Dr. Anirban Bandyopadhyay of Globalfoundries Inc. Please see below for the schedule and details of the talk. Topic: Differentiated Fully Depleted SOI (FDSOI) Technology for Highly Efficient and Integrated mmwave 5G Connectivity Solution Abstract: The emergence of enhanced mobile broadband (eMBB) connectivity based on mmwave 5G generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband, it also poses a lot of technical challenges in terms of coverage, generating enough transmitted power efficiently particularly in the uplink, system cost & scaling and long term reliability of the hardware system particularly for  infrastructure including Satellite born systems. Current talk will focus on how Silicon technologies based on differentiated fully depleted SOI (FDSOI) can address the above challenges by enabling a highly efficient and integrated radio without compromising on the mmwave performance and reliability. Talk will highlight the technology Figures of Merits (FOMs) for a mmwave phased array system and how a differentiated FDSOI technology platform compares with other silicon technologies in terms of devices and circuits. Speaker: Dr. Anirban Bandyopadhyay of GLOBALFOUNDRIES INC. Biography: Dr. Anirban Bandyopadhyay is the Senior Directorof Strategic Applications within the Mobility & Wireless Infrastructure Business Unit of GLOBALFOUNDRIES, USA. His work is currently focused on hardware architecture & technology evaluations for emerging RF and mmwave applications. Prior to joining GLOBALFOUNDRIES, he was with IBM Microelectronics, New York and with Intel, California where he worked on different areas like RF Design Enablement, Silicon Photonics, signal integrity in RF & Mixed signal SOC’s. Dr. Bandyopadhyay did his PhD in Electrical Engineering from Tata Institute of Fundamental Research, India and Post-Doctoral research at Nortel, Canada and at Oregon State University, USA. He represents Global Foundries in different industry consortia and alliances on RF/mmwaveapplications and is a Distinguished Lecturer of IEEE Electron Devices Society.

The Circuits & Devices Chapter of IEEE Toronto is pleased to invite you to join us for a virtual talk by Distinguished Lecturer Dr. Durga Misra of the New Jersey Institute of Technology. Please see below for schedule and details. Topic: Self-Heating in FinFETs: Characterization, Reliability and Impact on Logic Circuits Abstract: Device scaling for sub-10 nm CMOS technology has introduced bulk/SOI FinFETs This talk will outline the self-heating (SH) in FinFETs and its characterization. Local self-heating can potentially affect device performance and exacerbate the effects of some reliability mechanisms. Three different measurement methodologies for the electrical characterization of FinFET self-heating at wafer-level will be described. Also, the impact of self-heating on reliability testing at DC conditions as well as realistic CMOS logic operating (AC) conditions will be discussed. Front-end-of-line (FEOL) reliability mechanisms, such as hot carrier injection (HCI) and non-uniform time dependent dielectric breakdown (TDDB) will also be outlined. Self-heating is also studied at more realistic device switching conditions in logic circuits by utilizing ring oscillators with several densities and stage counts. The measurements indicate that self-heating is considerably lower in logic circuits compared to constant voltage stress conditions and degradation is not distinguishable. Speaker: Prof. Durga Misra, Department of Electrical and Computer Engineering, New Jersey Institute of Technology Biography: Prof. Durga Misra is a Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, USA. His current research interests are in the areas of nanoelectronic/optoelectronic devices and circuits; especially in the area of nanometer CMOS gate stacks and device reliability. He is a Fellow of IEEE and is currently a Distinguished Lecturer of IEEE Electron Devices Society (EDS) and served in the IEEE EDS Board of Governors. He is a Fellow of the Electrochemical Society (ECS). He received the Thomas Collinan Award from the Dielectric Science & Technology Division of ECS. He is also the winner of the Electronic and Photonic Division Award from ECS. He edited and co-edited more than 45 books and conference proceedings in his field of research. He has published more than 200 technical articles in peer reviewed Journals and in International Conference proceedings including 95 Invited Talks. He has graduated 19 PhD students and 40 MS students. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1985 and 1988, respectively.

The Circuits & Devices Chapter of IEEE Toronto is pleased to invite you to join us for a virtual talk by Distinguished Lecturer Dr. Andrew Mason of the Michigan State University. Topic: Augmented Perception: Next Generation Wearables and Human-Machine Interfaces Abstract: Products like Fitbit and the Apple Watch have brought to the public decades of foundational work on wearable technologies achieved by researchers in the IEEE CAS Society and related groups. Similarly, research into brain- and human-machine interface is starting to enter the public domain in applications including deep brain stimulation, prosthetic limb control, and human assistive devices. While researchers continue to explore new wearable sensing and human-interface paradigms, it is vital that we also explore what applications the next generation of wearable human-machine interfaces can and should enable. This talk will review key challenges and approaches within wearable assistive device and brain/human interface technologies. Aspects of physiological, environmental, and behavioral sensing within wearable platforms will be discussed, and technical challenges will be highlighted. Finally, the next generation concept of augmented human perception, real time machine-enhanced awareness that expands natural human senses, will be introduced. Utilizing wearable sensing and real-time feedback through visual, audio and tactile mechanism, augmented perception is poised to revolutionize the human experience, enhance daily performance, and enable new pathways to address mental and physical health concerns. Speaker: Andrew Mason of Michigan State University Biography: Andrew J. Mason received the BS in Physics with highest distinction from Western Kentucky University in 1991, the BSEE with honors from the Georgia Institute of Technology in 1992, and the MS and Ph.D. in Electrical Engineering from The University of Michigan, Ann Arbor in 1994 and 2000, respectively. From 1999 to 2001 he was an Assistant Professor at the University of Kentucky.  In 2001 he joined the Department of Electrical and Computer Engineering at Michigan State University in East Lansing, Michigan, where he is currently a Professor.  His research explores mixed-signal circuits, microfabricated structures and machine learning algorithms for integrated microsystems in biomedical, environmental monitoring and sustainable lifestyle applications.  Current projects are focused on design of augmented human awareness systems including signal processing algorithms and hardware for brain-machine interface, wearable/implantable biochemical and neural sensors, and lab-on-CMOS integration of sensing, instrumentation, and microfluidics. Dr. Mason is a Senior Member of the Institute of Electrical and Electronic Engineers (IEEE) and serves on the Sensory Systems and Biomedical Circuits and Systems Technical Committees of the IEEE Circuits and Systems Society. He is an Associate Editor for the IEEE Trans. Biomedical Circuits and Systems and regularly serves on the technical and review committees for several IEEE conferences. Dr. Mason was co-General Chair of the 2011 IEEE Biomedical Circuits and Systems Conference. He is a recipient of the 2006 Michigan State University Teacher-Scholar Award and the 2010 Withrow Award for Teaching Excellence. Email: mason@msu.edu

The Circuits & Devices Chapter of IEEE Toronto is pleased to invite you to join us for a virtual talk by Dr. Hesham Omran of Ain Shams University. This event will be a virtual talk held on Zoom. The invitation will be sent to registerants. Topic: The Analog Designer's Toolbox (ADT): Towards A New Paradigm for Analog IC Design Abstract: The integrated circuit (IC) technology has witnessed an exponential advancement in the last decades and has changed every aspect in our life. On the other hand, the analog IC design flow did not experience any major change since the introduction of Berkeley SPICE in the 1970s, posing significant challenges to the design of complex systems and to the transfer of analog design expertise and knowledge. The Analog Designer’s Toolbox (ADT) is an analog EDA tool that addresses this problem by defining a new paradigm in analog IC design. ADT provides a turnkey solution that enables everyone to reap the benefits of the gm/ID design methodology powered by precomputed lookup tables (LUTs). At the device level, ADT Device Xplore gives an easy interface to plot arbitrary design charts involving complex expressions. The designer can explore devices from different technologies at different corners and temperatures, and extract simulator-accurate design points while taking second-order effects into consideration. At the block level, ADT Design Xplore gives the designer the power of design space exploration, constraints management, live tuning, and optimization, all in a single cockpit without invoking the simulator. Moreover, with a single click, ADT can build the testbenches in the background and report the results from your favorite simulator. The aim of ADT is to boost productivity, restore designer’s intuition, and make the design process systematic, optimized, and fun! Speaker: Hesham Omran Biography: Dr. Hesham Omran received the B.Sc. (with honors) and M.Sc. degrees from Ain Shams University, Cairo, Egypt, in 2007 and 2010, respectively, and the Ph.D. degree from King Abdullah University of Science and Technology (KAUST), Saudi Arabia, in 2015, all in Electrical Engineering. From 2008 to 2011, he was a Design Engineer with Si-Ware Systems (SWS), Cairo, Egypt, where he worked on the circuit and system design of the first miniaturized FT-IR MEMS spectrometer (NeoSpectra), and a Research and Teaching Assistant with the Integrated Circuits Lab (ICL), Ain Shams University. From 2011 to 2016 he was a Researcher with the Sensors Lab, KAUST. He held internships with Bosch Research and Technology Center, CA, USA, and with Mentor Graphics, Cairo, Egypt. In 2016, he rejoined the ICL, Ain Shams University, as an Assistant Professor. He developed and taught several advanced courses on different topics in the field of IC Design. Most of these courses are available on the Mastering Microelectronics YouTube channel with 4k+ subscribers. He co-founded Master Micro in 2020 to develop the Analog Designer’s Toolbox (ADT), a winner of the Egyptian ITIDA-TIEC startup incubation program. Dr. Hesham has received several awards including the Egyptian State Encouragement Award for Engineering Sciences in 2019, best paper award from the IEEE International Design and Test Conference in 2009, and Academic Excellence Awards from KAUST and Ain Shams University in 2011 and 2002, respectively. He has published 40+ papers in international journals and conferences. He serves as a reviewer for several international journals and conferences including IEEE Transactions on Circuits and Systems (TCAS) I & II, IEEE Transactions on Instrumentation and Measurement, and IEEE Transactions on Very Large Scale Integration Systems (TVLSI). His research interests are in the design of analog and mixed-signal integrated circuits, and especially in analog and mixed-signal CAD tools and design automation. Email: hesham.omran@master-micro.com

The lecture is composed of two one-hour parts. In Part I a general overview of SSR/IFF is presented which includes a review of terms and definitions. From there, a historical timeline of SSR/IFF is summarized beginning with early implementations and ending with modern day systems. Then system architectures are reviewed starting with block diagrams and the challenges of scanning airspace. System-level features discussed include sidelobe suppression, antenna dwell time, azimuth determination and RF link budgets. In addition, the trade-offs between 2-channel and 3-channel systems are reviewed. Link to virtual event will be provided after registration. Contact: IEEE Long Island CAS Society Speaker(s): Frank Messina Biography: Frank Messina is the Chief Engineer of the SSR and IFF products for Telephonics. Frank has 50 years of experience in the design, development, and fielding of innovative IFF and SSR products for Military and Civil use. Frank is the lead IFF Interrogator Systems Engineer for the world’s fleet of AWACS aircraft, US Navy P8-A Multi-Mission Aircraft (MMA), US Navy MH-60R aircraft, Canadian Maritime Patrol Aircraft (CP140), Canadian Maritime Helicopter (MHP), Canadian Frigate Upgrade, USMC G/ATOR, USAF D-RAPCON, Mode 5 Operational Autonomous Surveillance (M5 OAS), SAAB Giraffe Mobile Platforms and other ground, shipboard and airborne based products at Telephonics. Earlier in his career, Frank was the lead engineer for the FAA Common Digitizer 2 (CD-2) SSR Beacon Extractor System. Frank was also instrumental in adding full Mode S interrogator capability to the NATO AWACS, which represents the first military IFF interrogator system to integrate the high-priority AEW Military IFF Modes with Mode S. He was also the IFF team leader for the design and development of the AN/APS-147 and AN/APS-153 IFF interrogator system – the first integrated and tightly-coupled Multi-Mode Radar and IFF interrogator fusion system. More recently, Frank lead the design and development of the AN/UPR-4(V) Passive Detection and Reporting System (PDRS) and Small Form Factor SFF-44 All-Mode Active and Passive IFF system.

Most of the existing circuit design methodologies are based on iterative methods, which are very time consuming and sometimes far from being optimal. The process of analog circuit design is generally so complex that most designers rely mainly on their own intuition to design and move toward an acceptable design point, which in many cases is based on a long process of trial-and-errors. There are two dominant circuit design methodologies used in academic institutions and industry: (1) Inversion-Coefficient (IC) method, and (2) Gm/IDS (GmID) approach. While IC method is more analytical, GmID require extensive device characterizations in order to create a comprehensive data-base describing device behavior in all modes of operations for different device sizes. Meanwhile, designers need to develop their own optimization scripts to search through all possible design points and select the best fit for their application, as these methodologies are not supported by the common EDA Tools. In this seminar, an improved design methodology will be introduced, which lies somewhere between the two approaches. Called C/IDS, the proposed design methodology requires prior knowledge on only few technology-dependent parameters, which are very easy to extract. Due to its analytical nature, this approach provides comprehensive design insight, while the flow of design can be automatized easily. Several examples will be provided to show effectiveness of the proposed algorithm for implementing energy and power efficient circuits. A set of data points demonstrating how performance of analog circuits evolve with technology scaling will be provided. Speaker(s): Armin Tajalli Register: https://events.vtools.ieee.org/m/314527 Biography:Armin Tajalli received his B.S. from Sharif University of Technology, Tehran, Iran, and the Ph.D. from Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland. He was part of the initiating team and a Senior Analog Architect with Kandou Bus, Lausanne, Switzerland, where he is currently the lead of the R&D Department. Since December 2017, he has joined as an Assistant Professor to the University of Utah, Salt Lake City, USA. He has published more than 90 articles in peer reviewed journals and conferences and holds 40 patents. He has received several awards, including The Best Paper Award in DesignCon (2016), PhD Prime Award at EPFL, Switzerland (2010), and IEEE AMD/CICC Scholarship (2009). He is currently serving as a Technical Program Committee (TPC) Member in IEEE CICC and ESSCIRC, and an Associate Editor of the IEEE Transactions on VLSI Systems.

[] Please note that this lecture has unfortunately had to be cancelled. Lecture notes from the talk will be shared with registrants. We sincerely apologize for the inconvenience. The IEEE Toronto Electronics Packaging Society is proud to present Distinguished Lecturer Dr. John Lau of Unimicron Technology Corporation and his talk on "Chiplet Design and Heterogeneous Integration Packaging". Abstract Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Heterogeneous integration uses packaging technology to integrate dissimilar chips, photonic devices, and/or components (either side-by-side, stacked, or both) with different sizes and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes and companies into a system or subsystem on a common package substrate. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for time-to-market, performance, form factor, power consumption or cost. In this lecture, the introduction, recent advances, and trends in chiplet design and heterogeneous integrationpackaging will be presented. Please join us Tuesday, December 13th at 11 AM in BA1240. The event will also be streamed live on Zoom for those who cannot attend in person. Food and refreshments will be served. Speaker(s): Dr. John H Lau, Bldg: Bahen Centre for Information Technology, 40 St George St, Room BA1240, Toronto, Ontario, Canada, M5S 2E4, Virtual: https://events.vtools.ieee.org/m/335514

For efficient design, verification and validation of integrated circuits and components it is important to have an easy to customize workflow. Python has become the standard programming language for machine learning, scientific computing and engineering. In this talk we describe the gdsfactory design automation tool. GDSfactory provides you an end to end workflow that combines layout, verification and validation, which is an extensible, open source, python driven flow for turning your chip designs into validated products. Speaker(s): Joaquin Matres, Ph.D., Virtual: https://events.vtools.ieee.org/m/348254