A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS
On Thursday, January 28, 2021 at 4:10 p.m., Ravi Shivnaraine will present give a talk, “A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS”. Day & Time: Thursday, January 28, 2021 4:10 p.m. – 5:00 p.m. Speaker(s): Ravi Shivnaraine of Rambus Organizer(s): IEEE Toronto Solid-State Circuits Society Location: Virtual – Zoom Contact: Saba Zargham Abstract: In this talk, Rambus will review their recent 26.5625Gbps to 106.25Gbps XSR SerDes macro in 7nm CMOS. The talk will go over the system architecture, self-test features, and measurement results. A 1.55pJ/b power efficiency and beachfront density of 722Gbps/mm have been achieved. Register: Please visit https://events.vtools.ieee.org/m/257895 to register and to view the Zoom link. Biography: Mr. Shivnaraine obtained his Bachelors and Masters from the University of Toronto in 2010 and 2012 respectively. Ravi has experience working on SerDes receivers at Snowbush, Huawei, and Rambus at 28Gbps, 56Gbps, and 112Gbps. Currently, he is at AnalogX working on next-generation SerDes in deep sub-micron nodes. His research interests are low power SerDes interfaces and digitally assisted analog techniques.