BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//IEEE Toronto Section - ECPv6.15.17//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
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REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
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BEGIN:STANDARD
TZOFFSETFROM:+0000
TZOFFSETTO:+0000
TZNAME:UTC
DTSTART:20250101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
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DTEND;TZID=UTC:20260210T160000
DTSTAMP:20260524T164407
CREATED:20260115T142113Z
LAST-MODIFIED:20260210T152108Z
UID:10000924-1770735600-1770739200@www.ieeetoronto.ca
SUMMARY:ADC Enhancement Techniques in Advanced CMOS Technologies
DESCRIPTION:Associate Professor\, Eindhoven University of Technology  E: P.J.A.Harpe@tue.nl Pieter Harpe (SM’15) received the MSc and PhD degrees from the Eindhoven University of Technology\, The Netherlands\, in 2004 and 2010\, respectively. In 2008\, he started as researcher at Holst Centre / imec\, The Netherlands\, where he worked on ultra low-power wireless transceivers\, with a focus on ADC research and design. In April 2011\, he joined Eindhoven University of Technology where he is currently an Associate Professor and lead of the Resource Efficient Electronics Lab. His main activities are on low-power analog and mixed-signal circuits\, for instance for biomedical applications\, internet of things\, and edge AI. Dr. Harpe is TPC member for ISSCC and A-SSCC\, Associate Editor for TCAS-I\, SSCS AdCom Member-at-Large and SSCS Distinguished Lecturer. He previously served as TPC member for ISSCC\, TPC member and track chair for ESSCIRC/ESSERC and co-organizer for AACD\, was an IEEE SSCS Distinguished Lecturer in 2016/2017\, and is recipient of the ISSCC 2015 Distinguished Technical Paper Award.  Abstract:The aim of this presentation is to introduce the basics and various practical illustrations of advanced ADC enhancement techniques in a nutshell. With applications pushing for higher resolutions & data-rates\, and technology-scaling favoring digital design\, the use of digital techniques to enhance ADC performance is inevitable. This talk will first summarize trends and trade-offs regarding the use of these digital-intensive techniques before illustrating some popular and recent examples from literature\, including calibration and enhancement techniques as well as digitally-inspired analog circuit design. Besides that\, an outlook is given regarding future challenges and opportunities in advanced CMOS technologies.  Refreshments will be provided!  Speaker(s): Pieter  Room: 303\, Bldg: Galbraith Building\, 35 St George Street\, Toronto\, Ontario\, Canada\, M5S1A4
URL:https://www.ieeetoronto.ca/event/adc-enhancement-techniques-in-advanced-cmos-technologies/
LOCATION:Room: 303\, Bldg: Galbraith Building\, 35 St George Street\, Toronto\, Ontario\, Canada\, M5S1A4
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