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BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230323T170000
DTEND;TZID=America/New_York:20230323T180000
DTSTAMP:20260417T073203
CREATED:20230315T141909Z
LAST-MODIFIED:20230402T172321Z
UID:10000613-1679590800-1679594400@www.ieeetoronto.ca
SUMMARY:THE ROLE OF CO-PACKAGED OPTICS IN OUR CONNECTED FUTURE
DESCRIPTION:Progress in computation and communication is increasingly bottlenecked by integrated circuit I/0. CMOS technology scaling has enabled the integration of hundreds of complete modems operating over 100Gbps on a single chip. Whereas optical links were previously reserved for communication over 100’s of kilometres\, they are now the primary solution for chip-to-chip links above 100 Gbps over any distance beyond a few metres. Co-packaged optics (CPO) bring optics right to the perimeter of our electronic integrated circuits\, and may therefore appear to be a natural continuation of this trend.\nIndeed\, PO holds the promise of simultaneously lowering system power consumption\, decreasing I/0 latency\, and increasing the total bandwidth of chip I/O. And yet\, at the same time\, it has the potential to increase the power density\, increase the cost\, and limit the bandwidth density of our\nchio I/O. This talk will clarify these seeming contradictions\, and paint a realistic picture of CPO’s role in future connectivity.\nCo-sponsored by: SPIE OPTICA Student Chapter\nSpeaker(s): Dr. Tony Chan Carusone\,\nRoom: GB119\, Bldg: Galbraith Building\, University of Toronto\, Toronto\, Ontario\, Canada
URL:https://www.ieeetoronto.ca/event/the-role-of-co-packaged-optics-in-our-connected-future/
LOCATION:Room: GB119\, Bldg: Galbraith Building\, University of Toronto\, Toronto\, Ontario\, Canada
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230202T160000
DTEND;TZID=America/New_York:20230202T170000
DTSTAMP:20260417T073203
CREATED:20221117T171950Z
LAST-MODIFIED:20230402T173319Z
UID:10000585-1675353600-1675357200@www.ieeetoronto.ca
SUMMARY:IoT Workshop for Pre-University Educators (Kick-Off Meeting)
DESCRIPTION:Network-based telemetry is embedded into virtually all modern products and systems in order to create new value for end users. Think of the Tesla automobile\, that can update its own operating software\, so the brakes work better! Pre-university ECE students need exposure to the hardware and protocols used in Internet-of-Things (“IoT”) enabled products\, as well as the special challenges of designing these products.\nThis 3-course\, 12-week workshop will help you incorporate networking concepts and technology into your curriculum\, and provide opportunities for your students to practice adding networking functionality to embedded projects. The courseware is based on a simple\, network-enabled line-following robot based on the Raspberry Pi Pico W board\, which will be provided to each participant.\nThis training is targeted towards Grade 11/12 Computer or Electronics Engineering Teachers (Ontario TEJ/ICS Curriculum)\, and will be delivered virtually using a Learning Management System\, combined with weekly live Q/A sessions to verify mastery of the material.\nWhen registering\, please complete all address fields\, so we can ship you a robot kit in time for the first session!\nTo learn more about the courses that will be covered in this workshop\, please visit the following page:\nhttps://www.cool-mcu.com/bundles/ieee-iot-workshop-for-pre-university-educators\nAgenda:\nKick-Off Meeting Agenda:\nOutcomes\nCourses & Topic Coverage\nIoT Robot Hardware Review\nUsing the LMS\nDetailed Training Schedule\nAssigned reading and lab exercise\nVirtual: https://events.vtools.ieee.org/m/328095
URL:https://www.ieeetoronto.ca/event/iot-workshop-for-pre-university-educators-kick-off-meeting/
LOCATION:Virtual: https://events.vtools.ieee.org/m/328095
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230123T161000
DTEND;TZID=America/New_York:20230123T170000
DTSTAMP:20260417T073203
CREATED:20230114T083732Z
LAST-MODIFIED:20230402T173509Z
UID:10000595-1674490200-1674493200@www.ieeetoronto.ca
SUMMARY:Distinguished Lecture Series: Wide Tuning-Range VCOs Using Multi-Mode Resonators
DESCRIPTION:LC VCOs are commonly used for RF carrier generation. A wide tuning range in a single VCO is desirable for covering multiple bands while occupying a small area. An octave tuning range enables continuous coverage of all lower frequencies by integer frequency division. LC VCOs are most often tuned using variable capacitor banks and varactors. Because of switch resistances in capacitor banks and poor quality factor of varactors\, using only capacitors for tuning degrades the phase noise\, especially at millimeter-wave frequencies. Variable inductors using series switches pose the same problem. Mutual coupling can be exploited to realize multiple resonant modes with different effective inductances without using switches. This allows a wider tuning range without substantial reduction in the tank quality factor. Topologies for multi-mode resonant structures and their performance will be described with examples from the literature.\nSpeaker(s): Dr. Krishnapura\,\nRoom: BA B025\, Bldg: Bahen Centre for Information Technology\, 40 St George St\, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/342962
URL:https://www.ieeetoronto.ca/event/distinguished-lecture-series-wide-tuning-range-vcos-using-multi-mode-resonators/
LOCATION:Room: BA B025\, Bldg: Bahen Centre for Information Technology\,  40 St George St\, Toronto\, Ontario\, Canada\,  M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/342962
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221216T084500
DTEND;TZID=America/New_York:20221216T163000
DTSTAMP:20260417T073203
CREATED:20221122T174709Z
LAST-MODIFIED:20230402T174228Z
UID:10000588-1671180300-1671208200@www.ieeetoronto.ca
SUMMARY:SSCS Workshop: Pushing the Frontiers in Wireline Communication
DESCRIPTION:Registration is free but required for this exciting in-person event.\nDetailed Agenda:\n08:45 – 09:10 Coffee\n09:10 – 09:15 Welcome Remarks: Dustin Dunwell\, Toronto SSCS Chapter Vice-Chair\n09:15 – 09:20 Opening Remarks: Ali Sheikholeslami\, SSCS VP Education\n09:20 – 10:20 Pushing the Energy Frontier in Wireline Communication – Davide Tonietto\, Huawei Canada\n10:20 – 10:40 Break\n10:40 – 11:20 Pushing the Data Rates in Wireline Communication – Ali Sheikholeslami\, University of Toronto\, Canada\n11:20 – 12:00 Error Propagation Detection and Correction in Wireline Communication – Hossein Shakiba\, Huawei Canada\n12:00 – 13:00 Lunch\n13:00 – 13:40 Short Reach Interconnects for the Emerging Multi-Die System Era – Dino Toffolon\, Synopys Canada\n13:40 – 14:20 Interconnect IP: Past\, Present\, and into the Future – Robert Wang\, Rambus Canada\n14:20 – 14:40 Break\n14:40 – 15:20 Trends in Wireline Communication – Kevin Parker\, Marvell\n15:20 – 16:00 Optimization Tools for Future Wireline Transceivers – Tony Chan Carusone\, University of Toronto\, Canada\, and Alphawave\n16:00 – 16:25 Panel Discussion\, Moderated by Dustin Dunwell\n16:25 – 16:30 Concluding Remarks\, Dustin Dunwell\nCo-sponsored by: University of Toronto\nRoom: SF1105\, Bldg: Sanford Fleming Building\, 10 King’s College Road\, University of Toronto\, Toronto\, Ontario\, Canada\, M5S 3G4
URL:https://www.ieeetoronto.ca/event/sscs-workshop-pushing-the-frontiers-in-wireline-communication/
LOCATION:Room: SF1105\, Bldg: Sanford Fleming Building\, 10 King’s College Road\, University of Toronto\, Toronto\, Ontario\, Canada\, M5S 3G4
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221121T180000
DTEND;TZID=America/New_York:20221121T193000
DTSTAMP:20260417T073203
CREATED:20221112T164712Z
LAST-MODIFIED:20230402T175428Z
UID:10000584-1669053600-1669059000@www.ieeetoronto.ca
SUMMARY:IEEE EDS Distinguished Lecture: Low Power Design and Predictive Failure Analytics in Silicon in nm Era
DESCRIPTION:Power has become the key driving force in processor as well AI specific accelerator designs as the frequency scale-up is reaching saturation. In order to achieve low power system\, circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale VLSI circuits. Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates.\nThis talk consists of pros and cons analysis on technology from power perspective and various techniques to exploit lower power. As the technology pushes towards sub-7nm era\, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power\, leakage power\, short circuit power and collision power are covered. Usage of clock gating\, power gating\, longer channel\, multi-Vt design\, stacking\, header-footer device techniques and other methods are described for logic and memory used for processors and AI. Finally the talk summarizes key challenges in achieving low power.\nIn addition the tutorial gives a brief overview of predictive failure analytics used in nm Technology. Process and environmental variations impact circuit behavior it is important to model their effects to build robust circuits. The tutorial describe how key statistical techniques can be effectively used to analyze and build robust circuits.\nSpeaker(s): Dr. Rajiv Joshi\,\nAgenda:\nThe event will start at 18:00PM EST and the talk will start at 18:10PM EST.\nRoom: BA2155\, Bldg: Bahen Centre for Information Technology\, 40 St George St \, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/331087
URL:https://www.ieeetoronto.ca/event/low-power-design-and-predictive-failure-analytics-in-silicon-in-nm-era/
LOCATION:Room: BA2155\, Bldg: Bahen Centre for Information Technology\, 40 St George St \, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/331087
CATEGORIES:Circuits & Devices,Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220421T161000
DTEND;TZID=America/New_York:20220421T170000
DTSTAMP:20260417T073203
CREATED:20220330T181903Z
LAST-MODIFIED:20220421T231238Z
UID:10000514-1650557400-1650560400@www.ieeetoronto.ca
SUMMARY:Wideband Digital-to-Analog Converters for mmWave Transmitter
DESCRIPTION:Over the past ten years\, the data rate of cellular communication networks has increased by 100x. The next-generation software-defined-radio based wireless transmission in mmWave bands demands multi-GHz bandwidth digital-to-analog conversion with medium to high resolution (e.g.\, 14-16 bit) and sampling rates beyond 10GS/s. The rate of bandwidth increase and the required improvements in energy efficiency have exceeded the benefits of CMOS process scaling alone. There are compelling needs for novel architecture and circuit design techniques. In this talk\, I will review recent development and present emerging parallel-path DAC architectures for extending the bandwidth with higher power and area efficiency than conventional interleaving designs. I will discuss the practical challenges along with several key analog design techniques. I will conclude with some future directions. At the end of the talk\, I will briefly introduce some other research activities in my group\, such as low power bioelectronics\, neural interfacing and modulation circuits\, and machine-learning accelerators. \nSpeaker(s): Dr. Xilin Liu \nVirtual: https://events.vtools.ieee.org/m/309574 \nBiography: Dr. Xilin Liu (Senior Member\, IEEE) is currently an Assistant Professor at the University of Toronto. He obtained his Ph.D. degree from the University of Pennsylvania. Before joining the University of Toronto in 2021\, he held industrial positions at Qualcomm Inc.\, where he conducted R&D of high-performance mixed-signal circuits for cellular communication. He led and contributed to the IPs that have been integrated into products in high-volume production\, including the industry’s first 5G chipset. He was a visiting scholar at Princeton University in 2014. He has co-authored two books along with over 30 peer-reviewed articles. He was the first author of the papers that have received the Best Student Paper Award at the 2017 ISCAS\, the Best Paper Award at the 2015 BioCAS\, the Best Track Award at the 2014 ISCAS\, and the student research preview (SRP) award at 2014 ISSCC. He also received the SSCS predoctoral achievement award at the 2016 ISSCC.
URL:https://www.ieeetoronto.ca/event/wideband-digital-to-analog-converters-for-mmwave-transmitter/
LOCATION:Toronto\, Ontario\, Canada\, Virtual: https://events.vtools.ieee.org/m/309574
CATEGORIES:Solid-State Circuits
ORGANIZER;CN="Dustin Dunwell":MAILTO:dustin.dunwell@gmail.com
END:VEVENT
BEGIN:VEVENT
DTSTART;VALUE=DATE:20210310
DTEND;VALUE=DATE:20210317
DTSTAMP:20260417T073203
CREATED:20210430T023726Z
LAST-MODIFIED:20210809T204929Z
UID:10000363-1615334400-1615939199@www.ieeetoronto.ca
SUMMARY:Integrated Broadband Analog Delay Circuits
DESCRIPTION:Recording: Click here to view Part I of the talk. \n\nThe humble analog delay is simple in principle but complicated in practice. Analog delays are useful in analog filters\, distributed amplifiers\, and time-interleaved or pipelined analog signal processing. Unfortunately\, it can be quite tricky to delay a continuous-time broadband analog waveform without distortion on an integrated circuit! Over the past two decades\, our lab has repeatedly encountered the need for integrated broadband analog delays and has done much work on their implementation. Now that CMOS technologies can readily process analog signals with 10’s of GHz of bandwidth\, analog delays less than one nanosecond are being used in new and creative ways. This talk reviews delay approximation and the implementation of delays from 10’s to 100’s of picoseconds having bandwidths up to 10’s of GHz. Case studies are presented using the analog delay circuits in FIR and IIR filters for wireline transceivers and in high-speed data converters. \nPart I\nDate: 10 Mar 2021 \nTime: 04:10 PM to 05:00 PM \nLocation: Virtual \nOrganizer(s): IEEE Toronto SSCS \nContact: Toronto Section Chapter\, SSC37 \nPart II\nDate: 16 Mar 2021 \nTime: 04:10 PM to 05:40 PM \nLocation: Virtual \nOrganizer(s): IEEE Toronto SSCS \nContact: Toronto Section Chapter\, SSC37 \n\nSpeaker(s): Anthony Chan Carusone \nBiography: Prof. Tony Chan Carusone has taught and researched integrated circuits and systems at the University of Toronto since completing his Ph.D. there in 2002. He and his graduate students have received seven best-paper awards at leading conferences for their work on chip-to-chip and optical communication circuits\, analog-to-digital conversion\, and precise clock generation. Prof. Chan Carusone was a Distinguished Lecturer for the IEEE Solid-State Circuits Society 2015-2017 and currently serves on the Technical Program Committee of the International Solid-State Circuits Conference. He has co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” along with D. Johns and K. Martin\, and “Microelectronic Circuits” along with A. Sedra and K.C. Smith. He was Editor-in-Chief of the IEEE Transactions on Circuits and Systems II: Express Briefs in 2009\, an Associate Editor for the IEEE Journal of Solid-State Circuits 2010-2017 and is now Editor-in-Chief of the IEEE Solid-State Circuits Letters.
URL:https://www.ieeetoronto.ca/event/integrated-broadband-analog-delay-circuits-part-ii/
LOCATION:Toronto\, Canada
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20210128T161000
DTEND;TZID=America/Toronto:20210128T170000
DTSTAMP:20260417T073203
CREATED:20210430T023720Z
LAST-MODIFIED:20210501T002303Z
UID:10000344-1611850200-1611853200@www.ieeetoronto.ca
SUMMARY:A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS
DESCRIPTION:On Thursday\, January 28\, 2021 at 4:10 p.m.\, Ravi Shivnaraine will present give a talk\, “A 26.5625Gbps to 106.25Gbps XSR SerDes with 1.55pJ/bit efficiency in 7nm CMOS”. \nDay & Time: Thursday\, January 28\, 2021\n4:10 p.m. – 5:00 p.m. \nSpeaker(s): Ravi Shivnaraine of Rambus \nOrganizer(s): IEEE Toronto Solid-State Circuits Society \nLocation: Virtual – Zoom \nContact: Saba Zargham \nAbstract: In this talk\, Rambus will review their recent 26.5625Gbps to 106.25Gbps XSR SerDes macro in 7nm CMOS. The talk will go over the system architecture\, self-test features\, and measurement results. A 1.55pJ/b power efficiency and beachfront density of 722Gbps/mm have been achieved. \nRegister: Please visit https://events.vtools.ieee.org/m/257895 to register and to view the Zoom link. \nBiography: Mr. Shivnaraine obtained his Bachelors and Masters from the University of Toronto in 2010 and 2012 respectively. Ravi has experience working on SerDes receivers at Snowbush\, Huawei\, and Rambus at 28Gbps\, 56Gbps\, and 112Gbps. Currently\, he is at AnalogX working on next-generation SerDes in deep sub-micron nodes. His research interests are low power SerDes interfaces and digitally assisted analog techniques.
URL:https://www.ieeetoronto.ca/event/a-26-5625gbps-to-106-25gbps-xsr-serdes-with-1-55pj-bit-efficiency-in-7nm-cmos/
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20181216T131000
DTEND;TZID=America/Toronto:20181216T143000
DTSTAMP:20260417T073203
CREATED:20210430T022124Z
LAST-MODIFIED:20210430T230005Z
UID:10000252-1544965800-1544970600@www.ieeetoronto.ca
SUMMARY:The Qubit is the Transistor: Si-based Transistor and Analog-Mixed-Signal Circuit Scaling and the Natural Progression of Moore’s Law to Silicon Quantum Computing at the Atomic Scale
DESCRIPTION:Monday December 17th\, 2018 at 1:10 p.m. Dr. Sorin Voinigescu\, Professor at the University of Toronto\, will be presenting a SSCS distinguished lecture: “The Qubit is the Transistor: Si-based Transistor and Analog-Mixed-Signal Circuit Scaling and the Natural Progression of Moore’s Law to Silicon Quantum Computing at the Atomic Scale”. \nDay & Time: Monday December 17th\, 2018\n1:10 p.m. ‐ 2:30 p.m. \nSpeaker: Dr. Sorin Voinigescu\nProfessor\, University of Toronto \nOrganizers: SSCS IEEE Toronto \nLocation: Bahen Centre\, Room BA1230\n40 St George St\, Toronto\, ON M5S 2E4 \nContact: Dustin Dunwell \nAbstract: Quantum computing is a hot topic at very cool temperatures. Cool as in 10-100 mK. \nRecently\, a cold-atom physicist nonchalantly asked me the question: Why are you interested in high temperature quantum computers? High as in 4 -12 K. He was serious! Need I talk about Global Warming in such cool environments? Pluto is another option. Today\, quantum computers consist of racks of microwave and analog-mixed-signal test equipment\, FPGAs and feedback loops for error correction\, long 50-Ohm coaxial cables\, and a few qubits formed with non-linear Josephson-junction resonators\, entangled through niobium superconducting λ/4 resonators at 8-20 GHz\, biased by a DC magnetic field of up to 1 Tesla\, and whose spin is controlled by an AC magnetic field rotating in the “lab frame”. Are you still spinning? \nThere’s talk of electrons as “microwave photons”\, Larmor and Rabi frequencies\, photon-to-spin entanglement\, RAP (as in rapid adiabatic passage)\, Bloch sphere\, tensors in n-dimensional Hilbert spaces\, but also of OFDM\, phase noise\, I-Q up- and down- conversion\, Gaussian pulse modulation\, coherent π/2\, π/4 spin phase rotations in azimuth and elevation. Qubits are logic gates and memory cells at the same time. Logic gate operations consist of synchronized microwave pulses applied sequentially to the same qubits. The only probabilistic part (need I mention Schrodinger’s cats Flip and Flop?) is readout\, when the spin state is projected on the Z (DC magnetic field) axis! \nIn other words\, quantum computing is about everything you learned and thought you’d never use again\, should have learned\, or you were never taught in undergrad and grad school in math\, quantum and atomic physics\, electronics\, electromagnetics\, and computer science… \nThis talk will first attempt to demystify and translate the physics of quantum computing to an electronics engineer jargon. Next\, I will discuss the feasibility of high-temperature (2-4 K) Si and SiGe electron/hole-spin qubits and qubit integrated circuits (ICs) in commercial 22nm FDSOI CMOS technology\, and explore their scalability through simulation to 2nm dimensions\, when the coupling energy\, ΔE\, becomes comparable to thermal noise at 77-300 K. \nSilicon electron-spin and hole-spin coupled quantum-dot (QD) qubits have attracted a lot of interest recently due to their potential for integration in commercial CMOS technology. However\, like their more established superconducting cousins\, to date\, because of the low confinement and coupling energies (e.g. ΔE\, in the tens of μeV range\, comparable to the thermal noise level\, kBT\, at 100 mK) their operation has been restricted to temperatures below 100 mK. Moreover\, since cryogenic systems cannot remove more than a few μW of thermal power at 100 mK\, and the experimental laboratory (think TNC at U of T versus TSMC 7nm fab) technologies in which these qubits have been realized do not allow for fabrication of spin manipulation and readout circuitry\, the latter reside on a separate chip\, at 4 K or higher temperature. The lack of monolithic integration further degrades readout fidelity and computing speed because the atto-Farad capacitance\, high-impedance qubit needs to drive 50Ω and 100x larger capacitance interconnect off- chip. A qubit with higher confinement and coupling energies\, with spin resonance in the upper mm-wave region\, will allow for higher temperature operation\, alleviating these problems and enabling large-scale monolithic quantum computing processors. For example\, a qubit operating at 4 K would require mode splitting energies of 0.25 meV which corresponds to a spin resonance frequency of 60 GHz and require a DC magnetic field of 2.5 T. Simplifying a bit\, 240GHz spin-resonance frequencies and 9T magnetic fields should be adequate for 12K operation and 1.4 THz with an humongous magnetic field are needed for 77 K. You get the drift…\nFinally\, I will briefly review hot-off-the-press results obtained here at U of T. For the first time we report (i) integration of qubits and electronics on the same die\, (ii) strained SiGe hole-spin and strained Si electron-spin FDSOI qubits on the same die\, and (iii) propose a monolithic processor architecture which allows for short\, 10-20ps spin control pulses and high Rabi frequencies\, fRabi\, to compensate for short spin phase coherence lifetime. We also demonstrate that\, at 2 K\, MOSFETs and cascodes can be operated as QDs in the subthreshold region while behaving as classical MOSFETs and cascodes in the saturation region\, suitable for qubits and mm-wave mixed-signal processing circuits\, respectively. \nIf we still have holiday time left\, I will go through a tutorial example of how we can derive the specification for the mm-wave spin manipulation and readout circuits starting from the Hamiltonian and the measured I-V characteristics of our SiGe hole-spin qubits. I may touch on the impact of minimum-size (18nmx6nmx80nm) MOSFET ofset voltage and process variation on qubit characteristics\, on spin manipulation and readout architectural options (low phase-noise radar\, OFDM radio\, low-noise\, broadband\, ultra-high-gain TIAs)\, mm-wave switch impact and OFDM sub-carrier spacing on qubit crosstalk and isolation…Or maybe we should leave that for New Years’.
URL:https://www.ieeetoronto.ca/event/the-qubit-is-the-transistor-si-based-transistor-and-analog-mixed-signal-circuit-scaling-and-the-natural-progression-of-moores-law-to-silicon-quantum-computing-at-the-atomic-scale/
LOCATION:Bahen Centre\, Room BA1230\, 40 St George St\, Toronto\, ON M5S 2E4
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20181122T160000
DTEND;TZID=America/Toronto:20181122T170000
DTSTAMP:20260417T073203
CREATED:20210430T022121Z
LAST-MODIFIED:20210430T225421Z
UID:10000143-1542902400-1542906000@www.ieeetoronto.ca
SUMMARY:Energy-Efficient Edge Computing for AI-driven Applications
DESCRIPTION:Thursday\, November 22nd 2018\, Vivienne Sze\, Associate Professor at MIT in the Electrical Engineering and Computer Science Department\, is presenting “Energy-Efficient Edge Computing for AI-driven Applications”. \nDay & Time: Thursday November 22nd\, 2018\n4:10 p.m. ‐ 5:00 p.m. \nSpeaker: Vivienne Sze\nAssociate Professor\, MIT in the Electrical Engineering and Computer Science Department \nOrganizers: IEEE Toronto Solid-State Circuits Society \nLocation: Sanford Fleming Building\, Room 1105\n10 King’s College Rd\nToronto\, Ontario\nCanada M5S 3G4 \nContact: Dustin Dunwell \nAbstract: Edge computing near the sensor is preferred over the cloud due to privacy and/or latency concerns for a wide range of applications including robotics/drones\, self-driving cars\, smart Internet of Things\, and portable/wearable electronics. However\, at the sensor there are often stringent constraints on energy consumption and cost in addition to throughput and accuracy requirements. In this talk\, we will describe how joint algorithm and hardware design can be used to reduce energy consumption while delivering real-time and robust performance for applications including deep learning\, computer vision\, autonomous navigation and video/image processing. We will show how energy-efficient techniques that exploit correlation and sparsity to reduce compute\, data movement and storage costs can be applied to various AI tasks including object detection\, image classification\, depth estimation\, super-resolution\, localization and mapping. \nBiography: Vivienne Sze is an Associate Professor at MIT in the Electrical Engineering and Computer Science Department. Her research interests include energy-aware signal processing algorithms\, and low-power circuit and system design for portable multimedia applications\, including computer vision\, deep learning\, autonomous navigation\, and video process/coding. Prior to joining MIT\, she was a Member of Technical Staff in the R&D Center at TI\, where she designed low-power algorithms and architectures for video coding. She also represented TI in the JCT-VC committee of ITU-T and ISO/IEC standards body during the development of High Efficiency Video Coding (HEVC)\, which received a Primetime Emmy Engineering Award. She is a co-editor of the book entitled “High Efficiency Video Coding (HEVC): Algorithms and Architectures” (Springer\, 2014). \nProf. Sze received the B.A.Sc. degree from the University of Toronto in 2004\, and the S.M. and Ph.D. degree from MIT in 2006 and 2010\, respectively. In 2011\, she received the Jin-Au Kong Outstanding Doctoral Thesis Prize in Electrical Engineering at MIT. She is a recipient of the 2018 Facebook Hardware & Software Systems Research Award\, the 2017 Qualcomm Faculty Award\, the 2016 Google Faculty Research Award\, the 2016 AFOSR Young Investigator Research Program (YIP) Award\, the 2016 3M Non-Tenured Faculty Award\, the 2014 DARPA Young Faculty Award\, the 2007 DAC/ISSCC Student Design Contest Award\, and a co-recipient of the 2017 CICC Outstanding Invited Paper Award\, the 2016 IEEE Micro Top Picks Award and the 2008 A-SSCC Outstanding Design Award. \nFor more information about research in the Energy-Efficient Multimedia Systems Group at MIT visit: http://www.rle.mit.edu/eems/
URL:https://www.ieeetoronto.ca/event/energy-efficient-edge-computing-for-ai-driven-applications/
LOCATION:Sandford Fleming Building\, 10 King’s College Rd\, Toronto\, ON M5S 3G4\, Canada
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20181115T133000
DTEND;TZID=America/Toronto:20181115T143000
DTSTAMP:20260417T073203
CREATED:20210430T022118Z
LAST-MODIFIED:20210430T225146Z
UID:10000246-1542288600-1542292200@www.ieeetoronto.ca
SUMMARY:SSCS Distinguished Lecture: Considerations and Implementations For High Data Rate Interconnect
DESCRIPTION:Thursday Nov 15\, 2018 at 1:30 p.m. Dr. Daniel Friedman\, Distinguished Research Staff Member\, IBM T.J. Watson Research Center\, will be presenting “SSCS Distinguished Lecture: Considerations and Implementations For High Data Rate Interconnect”. \nDay & Time: Thursday November 15th\, 2018\n1:30 p.m. ‐ 2:30 p.m. \nSpeaker: Dr. Daniel Friedman\nDistinguished Research Staff Member\nIBM T.J. Watson Research Center \nOrganizers: IEEE Toronto Solid-State Circuits Society \nLocation: Bahen Centre Room B024\n40 St. George Street\nToronto\, ON M5S 2E4 \nContact: Dustin Dunwell \nAbstract: Cloud computing requires many different interconnects. These links provide connectivity between and among CPUs\, accelerators\, memory\, and switches; each link comes with its own distance and bandwidth requirements. Wireline transceivers are responsible for sending and receiving data from one chip to and from another\, thus enabling required connectivity. Key specifications for such designs include data rate\, power consumption\, area\, and connection distance. Distance and data rate specifications\, in particular\, drive the choice of physical channel to be used for the connection\, which in turn drives requirements including the equalization capabilities of the transceiver. For short chip-to-chip channels with limited frequency-dependent loss\, simple transceivers with little or no integrated equalization are appropriate\, while for longer channels crossing backplanes and involving multiple transitions through connectors\, complex transceivers with adaptive transmit and receive equalization are the right choice. As connection distances grow even longer\, optical interconnect becomes an attractive option. In this talk\, a framework for understanding serial link design will be presented\, including a discussion of basic equalization strategies and key challenges. Next\, several design examples will be presented\, covering approaches to key classes of interconnect\, from short reach channels to backplane channels to enabling highly integrated optical approaches. The talk will conclude with a discussion of emerging directions in this field. \nBiography: Daniel Friedman is currently a Distinguished Research Staff Member and Senior Manager of the Communication Circuits and Systems department of the IBM Thomas J. Watson Research Center. He received his doctorate from Harvard University in 1992 and subsequently completed post-doctoral work at Harvard and consulting work at MIT Lincoln labs\, broadly in the area of image sensor design. After joining IBM in 1994\, he initially developed field-powered RFID tags before turning to high data rate wireline and wireless communication. His current research interests include high-speed I/O design\, PLL design\, mmWave circuits and systems\, and circuit/system approaches to enabling new computing paradigms. He was a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC\, the 2009 JSSC Best Paper Award (given in 2011)\, and the 2017 ISSCC Lewis Winner Outstanding Paper Award; he holds more than 50 patents and has authored or co-authored more than 75 publications. He was a member of the BCTM technical program committee from 2003-2008 and of the ISSCC international technical program committee from ISSCC 2009 through ISSCC 2016; he served as the Wireline sub-committee chair from ISSCC 2012 through ISSCC 2016. He has served as the Short Course Chair from ISSCC 2017 to the present and is a member of the SSCS Adcom since 2018.
URL:https://www.ieeetoronto.ca/event/sscs-distinguished-lecture-considerations-and-implementations-for-high-data-rate-interconnect/
LOCATION:Bahen Centre Room B024\, 40 St. George Street Toronto\, ON M5S 2E4
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20180810T100000
DTEND;TZID=America/Toronto:20180810T120000
DTSTAMP:20260417T073203
CREATED:20210430T014030Z
LAST-MODIFIED:20210430T224255Z
UID:10000229-1533895200-1533902400@www.ieeetoronto.ca
SUMMARY:IEEE SSCS/CAS Distinguished Lecture Series – Dr. Gabor Temes
DESCRIPTION:Friday\, August 10th 2018\, the IEEE Toronto SSCS/CAS invites you to the IEEE SSCS/CAS Distinguished Lecture Series on: “A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC” by Lukang Shi and Gabor C. Temes\, and “Noise Filtering and Linearization of Single-Ended Circuits” by Gabor C. Temes et al.\, School of EECS\, Oregon State University. \nDate: Friday August 10th\, 2018 \nOrganizers: IEEE Toronto SSCS/CAS \nLocation: Bahen Centre Room BA1210 \nLecture 1 (10:10am – 11:00am): A 13b ENOB Noise-Shaping SAR ADC with a Two-Capacitor DAC \nSpeakers: Lukang Shi and Gabor C. Temes\nSchool of EECS\, Oregon State University \nAbstract: An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted capacitors\, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus\, the capacitance spread in the DAC is much smaller than that of the conventional binary-weighted capacitor array\, and the mismatch error can be greatly reduced. The circuit provides first-order noise shaping\, which can improve the ADC’s linearity even for a small oversampling ratio. Also\, the proposed architecture uses a monotonic approximation procedure\, which requires fewer conversion steps than for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth\, it achieved a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing noise mitigation schemes and higher-order noise shaping. These topics will also be discussed. \nLecture 2 (11:10am – 12:00pm): Noise Filtering and Linearization of Single-Ended Circuits \nSpeakers: Gabor C. Temes et al.\nSchool of EECS\, Oregon State University \nAbstract: The performance of analog integrated circuits is often limited by the noise generated in its components. Several circuit techniques exist for suppressing the effects of the low-frequency noise. In this paper\, existing techniques are described for noise mitigation. Also\, a novel approach is proposed\, which can suppress low-frequency noise. In addition\, the new process will also reduce even-order distortion\, another major limitation of analog circuits. Finally\, it may allow the use of single-ended circuits in applications where usually differential structures are needed. \nBiography: Gabor C. Temes received the Ph.D. degree in electrical engineering from the University of Ottawa\, ON\, Canada\, in 1961\, and an honorary doctorate from the Technical University of Budapest\, Budapest\, Hungary\, in 1991. He held academic positions at the Technical University of Budapest\, Stanford University and the University of California at Los Angeles. He worked in industry at Northern Electric R&D Laboratories and at Ampex Corp. He is now a Professor in the School of Electrical Engineering and Computer Science at Oregon State University. \nDr. Temes received the IEEE Leon K. Kirchmayer Graduate Teaching Award in 1998\, and the IEEE Millennium Medal in 2000. He was the 2006 recipient of the IEEE Gustav Robert Kirchhoff Award\, and the 2009 IEEE CAS Mac Valkenburg Award. He received the 2017 Semiconductor Industry Association-SRC University Researcher Award. He is a member of the National Academy of Engineering.
URL:https://www.ieeetoronto.ca/event/ieee-sscs-cas-distinguished-lecture-series-dr-gabor-temes/
LOCATION:Bahen Centre for Information Technology\, St George St\, Toronto\, ON M5S 2E4\, Canada
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20170808T160000
DTEND;TZID=America/Toronto:20170808T170000
DTSTAMP:20260417T073203
CREATED:20210430T012918Z
LAST-MODIFIED:20210430T212239Z
UID:10000132-1502208000-1502211600@www.ieeetoronto.ca
SUMMARY:Design Considerations for Power Efficient Continuous-Time Delta Sigma ADCs
DESCRIPTION:Tuesday August 8\, 2017 at 4:10 p.m. Dr. Shanthi Pavan\, Professor of Electrical Engineering at the Indian Institute of Technology\, will be presenting “Design Considerations for Power Efficient Continuous-Time Delta Sigma ADCs”. \nRecording of the Event: https://drive.google.com/file/d/0B5wB8uI08dYvbmtnQjJoclF0VW8/view?usp=sharing \nDay & Time: Tuesday August 8\, 2017\n4:10 p.m. – 5:10 p.m. \nSpeaker: Dr. Shanthi Pavan\nProfessor of Electrical Engineering\nIndian Institute of Technology\, Madras \nLocation: Bahen Centre\, room BA1230\n40 St George St\, Toronto\, ON M5S 2E4 \nContact: Dustin Dunwell \nOrganizers: Solid-State Circuits Society \nAbstract: Continuous-time Delta-Sigma Modulators (CTDSMs) are a compelling choice for the design of high resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices\, many of which seem to pull in opposite directions. Further\, it is often difficult to make a clear comparison of various architectures\, as they have been designed for dissimilar specifications\, by different design groups\, and in different technology nodes. This talk examines various design alternatives for the design of power efficient single-loop continuous-time delta sigma converters. \nBiography: Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engineering from the Indian Institute of Technology\, Madras in 1995 and the Masters and Doctoral degrees from Columbia University\, New York in 1997 and 1999 respectively. He is now with the Indian Institute of Technology-Madras\, where he is a Professor of Electrical Engineering. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr.Pavan is the recipient of many awards for teaching and research\, including the IEEE Circuits and Systems Society Darlington Best Paper Award and the Shanti Swarup Bhatnagar Award (from the Government of India). He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I – Regular Papers. He is a Fellow of the Indian National Academy of Engineering.
URL:https://www.ieeetoronto.ca/event/design-considerations-for-power-efficient-continuous-time-delta-sigma-adcs/
LOCATION:Bahen Centre\, room BA1230
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20170609T140000
DTEND;TZID=America/Toronto:20170609T153000
DTSTAMP:20260417T073203
CREATED:20210430T012917Z
LAST-MODIFIED:20210430T211953Z
UID:10000066-1497016800-1497022200@www.ieeetoronto.ca
SUMMARY:RF Integrated Harmonic Oscillators in Silicon Technologies
DESCRIPTION:Friday June 9\, 2017 at 2:10 p.m. IEEE Distinguished Lecturer and Professor at Lund University Pietro Andreani will be presenting “RF Integrated Harmonic Oscillators in Silicon Technologies”. \nEvent Media:\nEvent Slides \nRecording of the Event \nDay & Time: Friday June 9\, 2017\n2:10 p.m. – 3:30 p.m. \nSpeaker: Dr. Pietro Andreani\nProfessor\, Lund University\nIEEE Distinguished Lecturer and Professor \nLocation: University of Toronto\n40 St. George Street\nToronto\, Ontario Canada\, M5S 2E4\nBahen Center of Information Technology\nRoom Number: B024 \nFree for everyone. Complimentary refreshments will be provided. \nContact: Dustin Dunwell \nOrganizers: Solid State Circuits Society \nAbstract: As one of the truly fundamental analog functions in any wireless/wireline application\, the voltage-controlled oscillator keeps attracting a great deal of well-deserved attention. In this presentation\, we will investigate the mechanisms of phase noise generation in harmonic oscillators\, including some recently published general results\, after which we will analyze both classical and emergent oscillator architectures\, describing pros and cons for each. Various techniques to achieve a very wide oscillator tuning range will be illustrated as well. \nBiography: Pietro Adreani received the M.S.E.E. degree from the University of Pisa\, Italy\, in 1988\, and the Ph.D. degree from Lund University\, Sweden\, in 1999. Between 2001 and 2007 he was chair professor at the Center for Physical Electronics\, Technical University of Denmark. From 2005 to 2014 he had a 20% position as analog/RF designer at Ericsson AB in Lund\, Sweden. Since 2007\, he has been associate professor at the department of Electrical and Information Technology (EIT)\, Lund University\, working analog/mixed-mode/RF IC design. He is also the head of the VINNOVA Center for System Design on Silicon\, hosted by EIT. He has been a TPC member of ISSCC (2007-2012)\, is a TPC member of ESSCIRC (chair of the Frequency Generation subcommittee since 2012\, TPC chair in 2014) and RFIC\, and Associate Editor of JSSC. He has been an IEEE SSCS Distinguished Lecturer since 2017. He has authored numerous papers on harmonic oscillators and phase noise.
URL:https://www.ieeetoronto.ca/event/rf-integrated-harmonic-oscillators-in-silicon-technologies/
LOCATION:Bahen Center of Information Technology\, Room Number: B024
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20170424T140000
DTEND;TZID=America/Toronto:20170424T153000
DTSTAMP:20260417T073203
CREATED:20210430T012914Z
LAST-MODIFIED:20210430T210922Z
UID:10000124-1493042400-1493047800@www.ieeetoronto.ca
SUMMARY:SSCS Distinguished Lecture: Holistic Design in Optical Interconnects
DESCRIPTION:Monday April 24\, 2017 at 2:10 p.m. Dr. Azita Emami\, Professor of Electrical Engineering and Medical Engineering at Caltech\, will be presenting a distinguished lecture\, “Holistic Design in Optical Interconnects”. \nDay & Time: Monday\, April 24th\, 2017\n2:10 p.m. – 3:30 p.m. \nSpeaker: Dr. Azita Emami\nProfessor of Electrical Engineering and Medical Engineering\nHeritage Medical Research Institute Investigator\nDeputy Chair of Division of Engineering and Applied Sciences\nCaltech \nLocation: Room B024\, Bahen Centre\n40 St. George Street\, Toronto\, ON M5S 2E4 \nContact: Dustin Dunwell \nOrganizers: IEEE Toronto SSCS \nCost: Free for everyone. Complimentary refreshments will be provided. \nAbstract: The scalability of CMOS technology has driven computation into a diverse range of applications across the power consumption\, performance and size spectra. Today Data Center (DC) and High Performance Computing (HPC) performance is increasingly limited by interconnection bandwidth. Maintaining continued aggregate bandwidth growth without overwhelming the power budget for these large scale computing systems and data centers is paramount. The historic power efficiency gains via CMOS technology scaling for such interconnects have rolled off over the past decade\, and new low-cost approaches are necessary. In this talk a number of promising solutions including Silicon-Photonic-based interconnects that can overcome these challenges will be discussed. In particular effective co-design of electronics and photonics as a holistic approach for reducing the total power consumption and enhancing the performance of the link will be presented. \nBiography: Azita Emami received her M.S. and Ph.D. degrees in Electrical Engineering from Stanford University in 1999 and 2004 respectively. She received her B.S. degree from Sharif University of Technology in 1996. Professor Emami joined IBM T. J. Watson Research Center in 2004 as a research staff member in the Communication Technologies Department. From Fall 2006 to Summer 2007\, she was an Assistant Professor of Electrical Engineering at Columbia University in the city of New York. In 2007\, she joined Caltech\, where she is now a Professor of Electrical Engineering and Medical Engineering. She is a Heritage Medical Research Institute Investigator\, and serves as the deputy chair of division of Engineering and Applied Sciences at Caltech. Her current research interests include mixed-signal integrated circuits and systems\, high-speed on-chip and chip-to-chip interconnects\, system and circuit design solutions for highly-scaled CMOS technologies\, wearable and implantable devices for neural recording\, stimulation\, and efficient drug delivery.
URL:https://www.ieeetoronto.ca/event/sscs-distinguished-lecture-holistic-design-in-optical-interconnects/
LOCATION:Room B024\, Bahen Centre 40 St. George Street\, Toronto\, ON M5S 2E4
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20170130T140000
DTEND;TZID=America/Toronto:20170130T150000
DTSTAMP:20260417T073203
CREATED:20210430T002612Z
LAST-MODIFIED:20210430T004643Z
UID:10000100-1485784800-1485788400@www.ieeetoronto.ca
SUMMARY:Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters
DESCRIPTION:Monday January 30\, 2017 at 2:10 p.m. Professor Carlos Saavedra\, Queen’s University and Associate Editor of the IEEE Transactions on Microwave Theory and Techniques\, will be presenting “Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters”. \nEvent Slides: Intermodulation Distortion Mitigation in Microwave Amplifiers and Frequency Converters  \nSpeaker: Professor Carlos Saavedra\nQueen’s University\, Kingston\nAssociate Editor of the IEEE Transactions on Microwave Theory and Techniques \nDay & Time: Monday\, January 30th\, 2017\n2:10 pm – 3:00 pm \nLocation: Room WB116\, Wallberg Building\n184 College St\, Toronto\, ON M5S 3E4 \nContact: Dustin Dunwell \nOrganizer: Solid State Circuit Society \nCost: Free for everyone.  Complimentary refreshments will be provided. \nAbstract: Intermodulation distortion (IMD) refers to the phenomenon where the spectral lines of an information‐bearing signal interact with themselves to yield new\, undesired\, spectral lines as they pass through a circuit. While some of the spurious tones are easily eliminated through filtering\, others are more difficult to deal with because they appear within the band of the information signal and interfere with it.  The study of IMD has a rich history and multiple techniques have been developed over time to mitigate it.  One such method is known as derivative superposition (DS)\, which reduces IMD distortion by using an auxiliary circuit to generate an out‐of‐phase replica of the IMD tones produced by the main circuit.  First introduced in the late 1990s\, DS has attracted much attention due to its small footprint and low power consumption.  This talk will discuss work we have carried out at Queen’s that uses DS and digital assist to improve the output third‐order intercept point (OIP3) of gallium‐nitride (GaN) power amplifiers from by +40 dBm to +50 dBm over a 5 GHz span.  A stand‐alone distortion cancelling cell will also be presented which can improve the OIP3 of a generic off‐the‐shelf microwave amplifier by 7.5 dB. The talk will conclude with a discussion of mixer linearization using DS and digital assist techniques. \nBiography: Carlos Saavedra obtained the Ph.D. degree from Cornell University\, Ithaca\, New York\, in 1998. From 1998 to 2000 he was a Senior Engineer at Millitech Corporation (North Hampton\, Massachusetts) and in 2000 he joined Queen’s University at Kingston where he currently holds the rank of Professor. He is an Associate Editor of the IEEE Transactions on Microwave Theory and Techniques\, is a member of the Technical Program Review Committee of the IEEE International Microwave Symposium (IMS) and of the Steering Committee of the IEEE NEWCAS conference.  He is Past Chair of the IEEE MTT‐S Technical Coordinating Committee (TCC‐22) on Signal Generation and Frequency Conversion and was Guest Editor of the September 2013 IEEE Microwave Magazine Focus Issue titled “100 Years of Mixer Technology”. He served on the Steering and Technical Program Committees of the 2012 IEEE IMS and was a member of the IEEE RFIC Symposium TPC from 2008 to 2011.  Prof. Saavedra is a three‐time recipient of the third‐year ECE undergraduate teaching award at Queen’s University.
URL:https://www.ieeetoronto.ca/event/intermodulation-distortion-mitigation-in-microwave-amplifiers-and-frequency-converters/
LOCATION:Room WB116\, Wallberg Building 184 College St\, Toronto\, ON M5S 3E4
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20161123T140000
DTEND;TZID=America/Toronto:20161123T150000
DTSTAMP:20260417T073203
CREATED:20210430T002609Z
LAST-MODIFIED:20210430T005626Z
UID:10000090-1479909600-1479913200@www.ieeetoronto.ca
SUMMARY:Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies
DESCRIPTION:Wednesday November 23\, 2016 at 2:10 p.m. Dr. Carlo Samori\, Professor at Politecnico di Milano\, Italy\, will be presenting “Phase Noise in LC Oscillators: From Basic Concepts to Advanced Topologies”. \nSpeaker: Dr. Carlo Samori\nProfessor\, Politecnico di Milano\, Italy \nDay & Time: Wednesday\, November 23\, 2016\n2:10 p.m. – 3:10 p.m. \nLocation: BA 1240\nBahen Centre for Information Technology\nUniversity of Toronto \nContact: Dustin Dunwell \nOrganizer: Solid State Circuit Society \nAbstract: Despite having been the subject of extensive study in last 20 years for the solid-state IC community\, the phase noise in voltage-controlled oscillators (VCOs) is still today an important research subject. The main reason is that phase noise is one of the main issues encountered during the design of a transceiver whose understanding is an essential know-how for an RF designer. A second reason is that the intrinsic time-variant nature of VCOs makes these circuits difficult to analyze\, therefore new topologies are often proposed\, claiming advantages in term of phase noise and/or dissipation that in several cases are hard both to understand and verify without a direct implementation. \nThis lecture will start from the basics of LC VCOs and of phase noise. The phase noise will be calculated in basic topologies and the fundamental trade-off with power dissipation and tuning range will be highlighted. The lecture then will continue by presenting advance VCO topologies\, showing how these circuits typically aim to enhance either the current or the voltage efficiency\, in order to improve the phase noise vs. power dissipation trade-off. \nBiography: Carlo Samori received the Ph.D. in electrical engineering in 1995\, at the Politecnico di Milano\, Italy\, where he is now a professor. His research interests are in the area of RF circuits\, in particular of design and analysis of VCOs and high performance frequency synthesizers. He has collaborated with several semiconductor companies. He is a co-author of more than 100 papers and of the book Integrated Frequency Synthesizers for Wireless Systems (Cambridge University Press\, 2007). Prof. Samori has been a member of the Technical Program Committee of the IEEE International Solid-State Circuits Conference and he is a member of the European Solid-State Circuits Conference. He has been Guest Editor for the December 2014 issue of the Journal of Solid-State Circuits.
URL:https://www.ieeetoronto.ca/event/phase-noise-in-lc-oscillators-from-basic-concepts-to-advanced-topologies/
LOCATION:BA 1240\, 40 St George Street\, University of Toronto
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20160526T140000
DTEND;TZID=America/Toronto:20160526T160000
DTSTAMP:20260417T073203
CREATED:20210429T230402Z
LAST-MODIFIED:20210430T001216Z
UID:10000017-1464271200-1464278400@www.ieeetoronto.ca
SUMMARY:Time Varying Circuits for Radio Receiver Applications
DESCRIPTION:Thursday May 26th\, 2016 at 2:10 p.m. Dr. Sudhakar Pamarti\, Associate Professor at the University of California\, will be presenting “Time Varying Circuits for Radio Receiver Applications”. \nSpeaker: Dr. Sudhakar Pamarti\nAssociate Professor\, University of California\, Los Angeles \nDay & Time: Thursday\, May 26th\, 2016\n2:10 p.m. \nLocation: Room BA 1210\nBahen Centre for Information Technology\nUniversity of Toronto\, St. George Campus\n40 St. George Street\, Toronto\, ON M5S 2E4 \nContact: Dustin Dunwell \nAbstract: Sharp\, programmable\, linear\, integrated filters are enabling components for software defined and cognitive radio applications. However\, they are difficult to realize: SAW and MEMS based filters are sharp and linear but not very programmable; active filters can be sharp and programmable but are not very linear; sampled charge domain filtering is sharp and programmable but the burden of the linearity is on the front end voltage-current converter. This talk descirbes an alternative approach that uses time-varying (as opposed to time-invariant) circuits to realize sharp\, programmable\, linear\, integrated filters. The technique exploits sampling aliases to effectively realize very sharp\, linear filtering prior to sampling. This talk will describe the basics of this time-varying circuit design approach and illustrates its application to radio front-ends and spectrum scanners. Measurement results from recent prototype integrated circuits will also be presented. \nBiography: Dr. Sudhakar Pamarti is an associate professor of electrical engineering at the University of California\, Los Angeles. He received the Bachelor of Technology degree in electronics and electrical communication engineering from the Indian Institute of Technology\, Kharagpur in 1995\, and the M.S. and the Ph.D. degrees in electrical engineering from the University of California\, San Diego in 1999 and 2003\, respectively. Prior to joining UCLA\, he has worked at Rambus Inc. (‘03-`05) and Hughes Software Systems (‘95-`97) developing high speed I/O circuits and embedded software and firmware for a wireless-in-local-loop communication system respectively. Dr. Pamarti is a recipient of the National Science Foundation’s CAREER award for developing digital signal conditioning techniques to improve analog\, mixed-signal\, and radio frequency integrated circuits. Dr. Pamarti serves as an Associate Editor of the IEEE Transactions on Circuits and Systems I: Regular Papers.
URL:https://www.ieeetoronto.ca/event/time-varying-circuits-for-radio-receiver-applications/
LOCATION:Room BA 1210 Bahen Centre for Information Technology University of Toronto\, St. George Campus 40 St. George Street\, Toronto\, ON M5S 2E4
CATEGORIES:Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20160311T160000
DTEND;TZID=America/Toronto:20160311T180000
DTSTAMP:20260417T073203
CREATED:20210429T230401Z
LAST-MODIFIED:20210430T000809Z
UID:10000026-1457712000-1457719200@www.ieeetoronto.ca
SUMMARY:Silicon Photonic Microring Resonator-Based Transceivers for Compact WDM Optical Interconnects
DESCRIPTION:Friday March 11th\, 2016 at 4:10 p.m. Dr. Samuel Palermo\, Associate Professor at Texas A&M University\, will be presenting “Silicon Photonic Microring Resonator-Based Transceivers for Compact WDM Optical Interconnects”. \nSpeaker: Dr. Samuel Palermo\, Associate Professor\nAssociate Professor\, Electrical and Computer Engineering Department\, Texas A&M\nIEEE Member and Associate Editor for IEEE Transactions on Circuits and Systems \nDay & Time: Friday\, March 11th\, 2016\nAt 4:10 p.m.\, with social hour after the talk at Prenup Pub\nRefreshments will be served at the pub \nLocation: BA1210\, Bahen Centre for Information Technology\, University of Toronto\n40 St George St\, Toronto\, ON M5S 2E4 \nContact: Dustin Dunwell \nAbstract: The rapid growth of I/O bandwidth in applications such as datacenters and supercomputers motivate the development of interconnect architectures that can dramatically scale bandwidth density in an energy-efficient manner. This talk examines the potential of silicon photonic microring resonator-based optical transceivers for compact wavelength-division multiplexing (WDM) optical interconnects. An overview of the photonic devices typically found in a ring resonator optical interconnect platform is provided and the design of transceiver circuits which address key challenges related to the modulators and drop filters is described. The possibility of further improvements in bandwidth density via efficient implementations of >50Gb/s PAM4 modulation with the microring modulators is detailed. \nBiography: Samuel Palermo received the B.S. and M.S. degree in electrical engineering from Texas A&M University\, College Station\, TX in 1997 and 1999\, respectively\, and the Ph.D. degree in electrical engineering from Stanford University\, Stanford\, CA in 2007. From 1999 to 2000\, he was with Texas Instruments\, Dallas\, TX\, where he worked on the design of mixed-signal integrated circuits for high-speed serial data communication. From 2006 to 2008\, he was with Intel Corporation\, Hillsboro\, OR\, where he worked on high-speed optical and electrical I/O architectures. In 2009\, he joined the Electrical and Computer Engineering Department of Texas A&M University where he is currently an associate professor. His research interests include high-speed electrical and optical interconnect architectures\, high performance clocking circuits\, and integrated sensor systems. \nDr. Palermo is a recipient of a 2013 NSF-CAREER award. He is a member of Eta Kappa Nu and IEEE. He currently serves as an associate editor for IEEE Transactions on Circuits and System – II and has served on the IEEE CASS Board of Governors from 2011 to 2012. He was a coauthor of the Jack Raper Award for Outstanding Technology-Directions Paper at the 2009 International Solid-State Circuits Conference and the Best Student Paper at the 2014 Midwest Symposium on Circuits and Systems. He received the Texas A&M University Department of Electrical and Computer Engineering Outstanding Professor Award in 2014 and the Engineering Faculty Fellow Award in 2015.
URL:https://www.ieeetoronto.ca/event/silicon-photonic-microring-resonator-based-transceivers-for-compact-wdm-optical-interconnects/
LOCATION:BA1210\, Bahen Centre for Information Technology\, University of Toronto
CATEGORIES:Solid-State Circuits
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BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20160226T110000
DTEND;TZID=America/Toronto:20160226T130000
DTSTAMP:20260417T073203
CREATED:20210429T230400Z
LAST-MODIFIED:20210430T000115Z
UID:10000012-1456484400-1456491600@www.ieeetoronto.ca
SUMMARY:Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables
DESCRIPTION:Friday February 26th\, 2016 at 11:10 a.m. Dr. Boris Murmann\, Associate Professor at Stanford University\, will be presenting “Systematic Design of Analog Circuits Using Pre-Computed Lookup Tables”. \nSpeaker: Dr. Boris Murmann\nAssociate Professor\, Electrical Engineering\, Stanford University\nIEEE Fellow\, and Program Vice-Chair at ISSCC 2016 \nDay & Time: Friday\, February 26th\, 2016\n11:10 a.m. – 12:40 p.m. \nLocation: BA1210\, Bahen Centre for Information Technology\, University of Toronto\n40 St George St\, Toronto\, ON M5S 2E4 \nContact: Dustin Dunwell \nAbstract: The majority of textbook material on analog circuit design is based on the square-law model for MOS transistors. While this model remains useful for teaching\, it has become too inaccurate for design in nanoscale CMOS. In circuit simulators\, this problem has been solved using complex models equations with hundreds of parameters. Since these descriptions are impractical for manual use\, designers tend to shy away from hand-analysis-based optimization and resort to a design style built on iterative and time-consuming “tweaking” in a simulator. This tutorial presents a systematic design methodology that bridges the gap between simulation\, hand analysis and script-based optimization. The approach hinges upon Spice-generated look-up tables containing the transistor’s equivalent model parameters (gm\, gds\, etc.) across a multi-dimensional sweep of the terminal voltages. We interpret and organize these data based on the transistor’s inversion level\, employing gm/ID as a proxy and key parameter for design. This width-independent metric captures a device’s efficiency in translating bias current to transconductance and spans nearly the same range in all modern CMOS processes (~3…30 S/A). When combined with other width-independent figures of merit (gm/Cgg\, gm/gds\, etc.) thinking in terms of gm/ID (rather than gate overdrive) allows us to study the tradeoffs between bandwidth\, noise\, distortion and power dissipation in a normalized space. The final bias currents and device sizes follow from a straightforward denormalization step using the current density ID/W. Since this entire flow is driven by Spice-generated data\, we maintain close agreement between the desired specs and the circuit’s simulated performance. We will detail the inner workings of this approach\, and showcase its capabilities using a variety of practical examples. \nBiography: Boris Murmann joined Stanford University in 2004\, where he currently serves as an Associate Professor of Electrical Engineering. He received the Ph.D. degree in electrical engineering from the University of California at Berkeley in 2003. From 1994 to 1997\, he was with Neutron Microelectronics\, Germany\, where he developed low-power and smart-power ASICs in automotive CMOS technology. Dr. Murmann’s research interests are in the area of mixed-signal integrated circuit design\, with special emphasis on data converters and sensor interfaces. In 2008\, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium in 2008 and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits and as the Data Converter Subcommittee Chair of the IEEE International Solid-State Circuits Conference (ISSCC). He currently serves as the program vice-chair for the ISSCC 2016. He is a Fellow of the IEEE.
URL:https://www.ieeetoronto.ca/event/systematic-design-of-analog-circuits-using-pre-computed-lookup-tables/
LOCATION:BA1210\, University of Toronto
CATEGORIES:Solid-State Circuits
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BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20160128T110000
DTEND;TZID=America/Toronto:20160128T120000
DTSTAMP:20260417T073203
CREATED:20210429T230359Z
LAST-MODIFIED:20210429T234329Z
UID:10000033-1453978800-1453982400@www.ieeetoronto.ca
SUMMARY:Linearization Techniques for Push-Pull Amplifiers
DESCRIPTION:Thursday January 28\, 2016 at 11:10 a.m. Dr. Rinaldo Castello\, IEEE Fellow\, will be presenting “Linearization Techniques for Push-Pull Amplifiers”. \nSpeaker: Dr. Rinaldo Castello\nIEEE Fellow\nUniversity of Pavia\, Italy \nDay & Time: Thursday\, January 28\, 2016\n11:10 a.m. \nLocation: University of Toronto\, Bahen Centre\, Room BA1230 \nOrganizer: Solid-State Circuits Society \nContact: Dustin Dunwell \nAbstract: Amplifiers that need to drive heavy loads (low resistances and/or large capacitances) or to handle high current signals with good efficiency generally use a push-pull output stage. This intrinsically creates large open-loop distortion components that need to be compressed through feedback to insure high closed-loop linearity. Minimizing close loop residual distortion involves three steps that will be discussed. First\, eliminate all open-loop source of distortion not intrinsic to the proper operation of the push pull structure. Second\, choose the amplifier topology that gives the maximum close loop compression of the open-loop distortion components for a given bandwidth. Third\, maximize the open-loop gain in the signal band and/or the unity gain bandwidth of the amplifier for a given topology while insuring stability in the presence of variable loads. \nBiography: Rinaldo Castello (S’78–M’78–SM’92–F’99) graduated from the University of Genova (summa cum laude) in 1977 and received the M.S. and the Ph. D. from the University of California\, Berkeley\, in ‘81 and ‘84. From ‘83 to ‘85 he was Visiting Assistant Professor at the University of California\, Berkeley. In 1987 he joined the University of Pavia where he is now a Full Professor. He consulted for ST-Microelectronics\, Milan\, Italy up to 2005 in ‘98 he started a joint research centre between the University of Pavia and ST and was its Scientific Director up to ‘05. He promoted the establishing of several design centre from multinational IC companies in the Pavia area among them Marvell for which he has been consulting from 2005. Rinaldo Castello has been a member of the TPC of the European Solid State Circuit Conference (ESSCIRC) since 1987 and of the International Solid State Circuit Conference (ISSCC) from ‘92 to ‘04. He was Technical Chairman of ESSCIRC ’91 and General Chairman of ESSCIRC ‘02\, Associate Editor for Europe of the IEEE J. of Solid-State Circ. from ’94 to ’96 and Guest Editor of the July ’92 special issue. From 2000 to 2007 he has been Distinguished Lecturer of the IEEE Solid State Circuit Society. Prof Castello was named one of the outstanding contributors for the first 50 and 60 years of ISSCC and a co-recipient of the Best Student Paper Award at the 2005 Symposium on VLSI of the Best Invited Paper Award at the 2011 CICC and of the Best Evening Panel Award at ISSCC 2012. He was one of the two European representatives at the Plenary Distinguished Panel of ISSCC 2013 and the Summer 2014 Issue of the IEEE Solid State Circuit Magazine was devoted to him. Rinaldo Castello is a Fellow of the IEEE.
URL:https://www.ieeetoronto.ca/event/linearization-techniques-for-push-pull-amplifiers/
LOCATION:University of Toronto\, Bahen Centre\, Room BA1230
CATEGORIES:Solid-State Circuits
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BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20151026T100000
DTEND;TZID=America/Toronto:20151026T110000
DTSTAMP:20260417T073203
CREATED:20210429T230356Z
LAST-MODIFIED:20210429T233819Z
UID:10000046-1445853600-1445857200@www.ieeetoronto.ca
SUMMARY:SSCS Distinguished Lecture: Cognitive Radio Transceiver Chips
DESCRIPTION:Monday October 26\, 2015 at 10:10 a.m. Eric Klumperink\, Ph.D. and IEEE Respected Lecturer\, will be presenting “Cognitive Radio Transceiver Chips”. \nPowerpoint from the Presentation:   \nSpeaker: Eric Klumperink\, Ph.D. \nIEEE Respected Lecturer\nTechnical Proram Committee Member of ISSCC and RFIC\nAssociate Professor\, Twente University\, Enschede \nDay & Time: Monday\, October 26\, 2015\n10:10 a.m. – 11:10 a.m. \nLocation: Room RS 211\, Rosebrugh Building\, University of Toronto\n164 College Street\, Toronto\, ON \nOrganizer: IEEE Toronto SSCS \nContact: Dustin Dunwell: dustin.dunwell@gmail.com \nRefreshments will be served. All are welcome. \nAbstract: A Cognitive Radio transceiver senses its radio environment and adaptively utilizes free parts of the radio spectrum. CMOS IC-technology is the mainstream technology to implement smart signal processing and for reasons of cost and size it is attractive to also integrate the radio frequency (RF) hardware in CMOS. This lecture discusses radio transceiver ICs designed for cognitive radio applications\, with focus on analog RF. Cognitive radio asks for new functionality\, e.g. spectrum sensing and more agility in the radio transmitter and flexibility in the receiver. Moreover\, the technical requirements on the building blocks are more challenging than for traditional single standard applications\, e.g. in bandwidth\, programmability\, sensing sensitivity\, blocker tolerance\, linearity and spurious emissions. Circuit ideas that address these challenges will be discussed\, and examples of chips and their achieved performance will be given. \nBiography: Eric Klumperink received his PhD from Twente University in Enschede\, The Netherlands\, in 1997. He is currently an Associate Professor at the same university where he teaches Analog and RF CMOS IC Design and guides research projects focussing on Cognitive Radio\, Software Defined Radio and Beamforming. Eric served as Associate Editor for TCAS-I and II\, and for the Journal of Solid-State Circuits. He is a technical program committee member of ISSCC and RFIC and is Respected Lecturer for IEEE. He holds several patents\, authored and co-authored more than 150 international refereed journal and conference papers\, and is a co-recipient of the ISSCC 2002 and the ISSCC 2009 “Van Vessem Outstanding Paper Award”.
URL:https://www.ieeetoronto.ca/event/sscs-distinguished-lecture-cognitive-radio-transceiver-chips/
LOCATION:Room RS 211\, Rosebrugh Building\, University of Toronto
CATEGORIES:Solid-State Circuits
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END:VCALENDAR