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BEGIN:VEVENT
DTSTART;TZID=America/New_York:20230317T130000
DTEND;TZID=America/New_York:20230317T140000
DTSTAMP:20260417T075829
CREATED:20230215T122244Z
LAST-MODIFIED:20230402T173203Z
UID:10000431-1679058000-1679061600@www.ieeetoronto.ca
SUMMARY:GDSfactory\, an Open Source flow for photonics & analog circuit design\, verification and validation
DESCRIPTION:For efficient design\, verification and validation of integrated circuits and components it is important to have an easy to customize workflow. Python has become the standard programming language for machine learning\, scientific computing and engineering.\nIn this talk we describe the gdsfactory design automation tool. GDSfactory provides you an end to end workflow that combines layout\, verification and validation\, which is an extensible\, open source\, python driven flow for turning your chip designs into validated products.\nSpeaker(s): Joaquin Matres\, Ph.D.\,\nVirtual: https://events.vtools.ieee.org/m/348254
URL:https://www.ieeetoronto.ca/event/gdsfactory-an-open-source-flow-for-photonics-analog-circuit-design-verification-and-validation/
LOCATION:Virtual: https://events.vtools.ieee.org/m/348254
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221213T110000
DTEND;TZID=America/New_York:20221213T123000
DTSTAMP:20260417T075829
CREATED:20221202T184923Z
LAST-MODIFIED:20230402T174817Z
UID:10000591-1670929200-1670934600@www.ieeetoronto.ca
SUMMARY:IEEE EPS Distinguished Lecture: Chiplet Design and Heterogeneous Integration Packaging
DESCRIPTION:[]\nPlease note that this lecture has unfortunately had to be cancelled. Lecture notes from the talk will be shared with registrants. We sincerely apologize for the inconvenience.\nThe IEEE Toronto Electronics Packaging Society is proud to present Distinguished Lecturer Dr. John Lau of Unimicron Technology Corporation and his talk on “Chiplet Design and Heterogeneous Integration Packaging”.\nAbstract\nChiplet is a chip design method and heterogeneous integration is a chip packaging method. Heterogeneous integration uses packaging technology to integrate dissimilar chips\, photonic devices\, and/or components (either side-by-side\, stacked\, or both) with different sizes and functions\, and from different fabless design houses\, foundries\, wafer sizes\, feature sizes and companies into a system or subsystem on a common package substrate. For the next few years\, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging\, whether it is for time-to-market\, performance\, form factor\, power consumption or cost. In this lecture\, the introduction\, recent advances\, and trends in chiplet design and heterogeneous integrationpackaging will be presented.\nPlease join us Tuesday\, December 13th at 11 AM in BA1240. The event will also be streamed live on Zoom for those who cannot attend in person.\nFood and refreshments will be served.\nSpeaker(s): Dr. John H Lau\,\nBldg: Bahen Centre for Information Technology\, 40 St George St\, Room BA1240\, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/335514
URL:https://www.ieeetoronto.ca/event/ieee-eps-distinguished-lecture-chiplet-design-and-heterogeneous-integration-packaging/
LOCATION:Bldg: Bahen Centre for Information Technology\, 40 St George St\, Room BA1240\, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/335514
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221121T180000
DTEND;TZID=America/New_York:20221121T193000
DTSTAMP:20260417T075829
CREATED:20221112T164712Z
LAST-MODIFIED:20230402T175428Z
UID:10000584-1669053600-1669059000@www.ieeetoronto.ca
SUMMARY:IEEE EDS Distinguished Lecture: Low Power Design and Predictive Failure Analytics in Silicon in nm Era
DESCRIPTION:Power has become the key driving force in processor as well AI specific accelerator designs as the frequency scale-up is reaching saturation. In order to achieve low power system\, circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale VLSI circuits. Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates.\nThis talk consists of pros and cons analysis on technology from power perspective and various techniques to exploit lower power. As the technology pushes towards sub-7nm era\, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power\, leakage power\, short circuit power and collision power are covered. Usage of clock gating\, power gating\, longer channel\, multi-Vt design\, stacking\, header-footer device techniques and other methods are described for logic and memory used for processors and AI. Finally the talk summarizes key challenges in achieving low power.\nIn addition the tutorial gives a brief overview of predictive failure analytics used in nm Technology. Process and environmental variations impact circuit behavior it is important to model their effects to build robust circuits. The tutorial describe how key statistical techniques can be effectively used to analyze and build robust circuits.\nSpeaker(s): Dr. Rajiv Joshi\,\nAgenda:\nThe event will start at 18:00PM EST and the talk will start at 18:10PM EST.\nRoom: BA2155\, Bldg: Bahen Centre for Information Technology\, 40 St George St \, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/331087
URL:https://www.ieeetoronto.ca/event/low-power-design-and-predictive-failure-analytics-in-silicon-in-nm-era/
LOCATION:Room: BA2155\, Bldg: Bahen Centre for Information Technology\, 40 St George St \, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/331087
CATEGORIES:Circuits & Devices,Solid-State Circuits
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20220603T160000
DTEND;TZID=America/New_York:20220603T170000
DTSTAMP:20260417T075829
CREATED:20220526T190131Z
LAST-MODIFIED:20220603T104757Z
UID:10000534-1654272000-1654275600@www.ieeetoronto.ca
SUMMARY:C/ID: A Design Methodology for Implementing Nanoscale Analog FET Circuits.
DESCRIPTION:Most of the existing circuit design methodologies are based on iterative methods\, which are very time consuming and sometimes far from being optimal. The process of analog circuit design is generally so complex that most designers rely mainly on their own intuition to design and move toward an acceptable design point\, which in many cases is based on a long process of trial-and-errors. There are two dominant circuit design methodologies used in academic institutions and industry: (1) Inversion-Coefficient (IC) method\, and (2) Gm/IDS (GmID) approach. While IC method is more analytical\, GmID require extensive device characterizations in order to create a comprehensive data-base describing device behavior in all modes of operations for different device sizes. Meanwhile\, designers need to develop their own optimization scripts to search through all possible design points and select the best fit for their application\, as these methodologies are not supported by the common EDA Tools. \nIn this seminar\, an improved design methodology will be introduced\, which lies somewhere between the two approaches. Called C/IDS\, the proposed design methodology requires prior knowledge on only few technology-dependent parameters\, which are very easy to extract. Due to its analytical nature\, this approach provides comprehensive design insight\, while the flow of design can be automatized easily. Several examples will be provided to show effectiveness of the proposed algorithm for implementing energy and power efficient circuits. A set of data points demonstrating how performance of analog circuits evolve with technology scaling will be provided. \nSpeaker(s): Armin Tajalli \nRegister: https://events.vtools.ieee.org/m/314527 \nBiography:Armin Tajalli received his B.S. from Sharif University of Technology\, Tehran\, Iran\, and the Ph.D. from Swiss Federal Institute of Technology (EPFL)\, Lausanne\, Switzerland. He was part of the initiating team and a Senior Analog Architect with Kandou Bus\, Lausanne\, Switzerland\, where he is currently the lead of the R&D Department. Since December 2017\, he has joined as an Assistant Professor to the University of Utah\, Salt Lake City\, USA. He has published more than 90 articles in peer reviewed journals and conferences and holds 40 patents. He has received several awards\, including The Best Paper Award in DesignCon (2016)\, PhD Prime Award at EPFL\, Switzerland (2010)\, and IEEE AMD/CICC Scholarship (2009). He is currently serving as a Technical Program Committee (TPC) Member in IEEE CICC and ESSCIRC\, and an Associate Editor of the IEEE Transactions on VLSI Systems.
URL:https://www.ieeetoronto.ca/event/c-id-a-design-methodology-for-implementing-nanoscale-analog-fet-circuits/
LOCATION:Virtual: https://events.vtools.ieee.org/m/314527
CATEGORIES:Circuits & Devices
ORGANIZER;CN="Wagih Ismail":MAILTO:wagih.ismail@ieee.org
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=UTC:20210622T180000
DTEND;TZID=UTC:20210622T190000
DTSTAMP:20260417T075829
CREATED:20210614T213828Z
LAST-MODIFIED:20210809T205336Z
UID:10000428-1624384800-1624388400@www.ieeetoronto.ca
SUMMARY:Overview of Secondary Surveillance Radar (SSR) and Identification Friend/Foe (IFF) Systems - Part I - Virtual Lecture - CEU/PDH Available
DESCRIPTION:The lecture is composed of two one-hour parts. \nIn Part I a general overview of SSR/IFF is presented which includes a review of terms and definitions. From there\, a historical timeline of SSR/IFF is summarized beginning with early implementations and ending with modern day systems. Then system architectures are reviewed starting with block diagrams and the challenges of scanning airspace. System-level features discussed include sidelobe suppression\, antenna dwell time\, azimuth determination and RF link budgets. In addition\, the trade-offs between 2-channel and 3-channel systems are reviewed. \nLink to virtual event will be provided after registration. \nContact: IEEE Long Island CAS Society \nSpeaker(s): Frank Messina \nBiography: \nFrank Messina is the Chief Engineer of the SSR and IFF products for Telephonics. Frank has 50 years of experience in the design\, development\, and fielding of innovative IFF and SSR products for Military and Civil use. Frank is the lead IFF Interrogator Systems Engineer for the world’s fleet of AWACS aircraft\, US Navy P8-A Multi-Mission Aircraft (MMA)\, US Navy MH-60R aircraft\, Canadian Maritime Patrol Aircraft (CP140)\, Canadian Maritime Helicopter (MHP)\, Canadian Frigate Upgrade\, USMC G/ATOR\, USAF D-RAPCON\, Mode 5 Operational Autonomous Surveillance (M5 OAS)\, SAAB Giraffe Mobile Platforms and other ground\, shipboard and airborne based products at Telephonics. \nEarlier in his career\, Frank was the lead engineer for the FAA Common Digitizer 2 (CD-2) SSR Beacon Extractor System. Frank was also instrumental in adding full Mode S interrogator capability to the NATO AWACS\, which represents the first military IFF interrogator system to integrate the high-priority AEW Military IFF Modes with Mode S. He was also the IFF team leader for the design and development of the AN/APS-147 and AN/APS-153 IFF interrogator system – the first integrated and tightly-coupled Multi-Mode Radar and IFF interrogator fusion system. More recently\, Frank lead the design and development of the AN/UPR-4(V) Passive Detection and Reporting System (PDRS) and Small Form Factor SFF-44 All-Mode Active and Passive IFF system.
URL:https://www.ieeetoronto.ca/event/overview-of-secondary-surveillance-radar-ssr-and-identification-friend-foe-iff-systems-part-i-virtual-lecture-ceu-pdh-available/
LOCATION:Virtual
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20210521T150000
DTEND;TZID=America/Toronto:20210521T160000
DTSTAMP:20260417T075829
CREATED:20210504T165404Z
LAST-MODIFIED:20210809T204727Z
UID:10000410-1621609200-1621612800@www.ieeetoronto.ca
SUMMARY:The Analog Designer's Toolbox (ADT): Towards A New Paradigm for Analog IC Design
DESCRIPTION:The Circuits & Devices Chapter of IEEE Toronto is pleased to invite you to join us for a virtual talk by Dr. Hesham Omran of Ain Shams University. \nThis event will be a virtual talk held on Zoom. The invitation will be sent to registerants. \nTopic: The Analog Designer’s Toolbox (ADT): Towards A New Paradigm for Analog IC Design \nAbstract: \nThe integrated circuit (IC) technology has witnessed an exponential advancement in the last decades and has changed every aspect in our life. On the other hand\, the analog IC design flow did not experience any major change since the introduction of Berkeley SPICE in the 1970s\, posing significant challenges to the design of complex systems and to the transfer of analog design expertise and knowledge. The Analog Designer’s Toolbox (ADT) is an analog EDA tool that addresses this problem by defining a new paradigm in analog IC design. ADT provides a turnkey solution that enables everyone to reap the benefits of the gm/ID design methodology powered by precomputed lookup tables (LUTs). At the device level\, ADT Device Xplore gives an easy interface to plot arbitrary design charts involving complex expressions. The designer can explore devices from different technologies at different corners and temperatures\, and extract simulator-accurate design points while taking second-order effects into consideration. At the block level\, ADT Design Xplore gives the designer the power of design space exploration\, constraints management\, live tuning\, and optimization\, all in a single cockpit without invoking the simulator. Moreover\, with a single click\, ADT can build the testbenches in the background and report the results from your favorite simulator. The aim of ADT is to boost productivity\, restore designer’s intuition\, and make the design process systematic\, optimized\, and fun! \nSpeaker: Hesham Omran \nBiography: \nDr. Hesham Omran received the B.Sc. (with honors) and M.Sc. degrees from Ain Shams University\, Cairo\, Egypt\, in 2007 and 2010\, respectively\, and the Ph.D. degree from King Abdullah University of Science and Technology (KAUST)\, Saudi Arabia\, in 2015\, all in Electrical Engineering. From 2008 to 2011\, he was a Design Engineer with Si-Ware Systems (SWS)\, Cairo\, Egypt\, where he worked on the circuit and system design of the first miniaturized FT-IR MEMS spectrometer (NeoSpectra)\, and a Research and Teaching Assistant with the Integrated Circuits Lab (ICL)\, Ain Shams University. From 2011 to 2016 he was a Researcher with the Sensors Lab\, KAUST. He held internships with Bosch Research and Technology Center\, CA\, USA\, and with Mentor Graphics\, Cairo\, Egypt. In 2016\, he rejoined the ICL\, Ain Shams University\, as an Assistant Professor. He developed and taught several advanced courses on different topics in the field of IC Design. Most of these courses are available on the Mastering Microelectronics YouTube channel with 4k+ subscribers. He co-founded Master Micro in 2020 to develop the Analog Designer’s Toolbox (ADT)\, a winner of the Egyptian ITIDA-TIEC startup incubation program. \nDr. Hesham has received several awards including the Egyptian State Encouragement Award for Engineering Sciences in 2019\, best paper award from the IEEE International Design and Test Conference in 2009\, and Academic Excellence Awards from KAUST and Ain Shams University in 2011 and 2002\, respectively. He has published 40+ papers in international journals and conferences. He serves as a reviewer for several international journals and conferences including IEEE Transactions on Circuits and Systems (TCAS) I & II\, IEEE Transactions on Instrumentation and Measurement\, and IEEE Transactions on Very Large Scale Integration Systems (TVLSI). His research interests are in the design of analog and mixed-signal integrated circuits\, and especially in analog and mixed-signal CAD tools and design automation. \nEmail: hesham.omran@master-micro.com
URL:https://www.ieeetoronto.ca/event/the-analog-designers-toolbox-adt-towards-a-new-paradigm-for-analog-ic-design/
LOCATION:Virtual – Zoom
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20210416T120000
DTEND;TZID=America/Toronto:20210416T130000
DTSTAMP:20260417T075829
CREATED:20210430T023730Z
LAST-MODIFIED:20210809T204407Z
UID:10000372-1618574400-1618578000@www.ieeetoronto.ca
SUMMARY:CAS Distinguished Lecture - Augmented Perception: Next Generation Wearables and Human-Machine Interfaces
DESCRIPTION:The Circuits & Devices Chapter of IEEE Toronto is pleased to invite you to join us for a virtual talk by Distinguished Lecturer Dr. Andrew Mason of the Michigan State University. \nTopic: Augmented Perception: Next Generation Wearables and Human-Machine Interfaces \nAbstract: \nProducts like Fitbit and the Apple Watch have brought to the public decades of foundational work on wearable technologies achieved by researchers in the IEEE CAS Society and related groups. Similarly\, research into brain- and human-machine interface is starting to enter the public domain in applications including deep brain stimulation\, prosthetic limb control\, and human assistive devices. While researchers continue to explore new wearable sensing and human-interface paradigms\, it is vital that we also explore what applications the next generation of wearable human-machine interfaces can and should enable. This talk will review key challenges and approaches within wearable assistive device and brain/human interface technologies. Aspects of physiological\, environmental\, and behavioral sensing within wearable platforms will be discussed\, and technical challenges will be highlighted. Finally\, the next generation concept of augmented human perception\, real time machine-enhanced awareness that expands natural human senses\, will be introduced. Utilizing wearable sensing and real-time feedback through visual\, audio and tactile mechanism\, augmented perception is poised to revolutionize the human experience\, enhance daily performance\, and enable new pathways to address mental and physical health concerns. \nSpeaker: Andrew Mason of Michigan State University \nBiography: \nAndrew J. Mason received the BS in Physics with highest distinction from Western Kentucky University in 1991\, the BSEE with honors from the Georgia Institute of Technology in 1992\, and the MS and Ph.D. in Electrical Engineering from The University of Michigan\, Ann Arbor in 1994 and 2000\, respectively. From 1999 to 2001 he was an Assistant Professor at the University of Kentucky.  In 2001 he joined the Department of Electrical and Computer Engineering at Michigan State University in East Lansing\, Michigan\, where he is currently a Professor.  His research explores mixed-signal circuits\, microfabricated structures and machine learning algorithms for integrated microsystems in biomedical\, environmental monitoring and sustainable lifestyle applications.  Current projects are focused on design of augmented human awareness systems including signal processing algorithms and hardware for brain-machine interface\, wearable/implantable biochemical and neural sensors\, and lab-on-CMOS integration of sensing\, instrumentation\, and microfluidics. \nDr. Mason is a Senior Member of the Institute of Electrical and Electronic Engineers (IEEE) and serves on the Sensory Systems and Biomedical Circuits and Systems Technical Committees of the IEEE Circuits and Systems Society. He is an Associate Editor for the IEEE Trans. Biomedical Circuits and Systems and regularly serves on the technical and review committees for several IEEE conferences. Dr. Mason was co-General Chair of the 2011 IEEE Biomedical Circuits and Systems Conference. He is a recipient of the 2006 Michigan State University Teacher-Scholar Award and the 2010 Withrow Award for Teaching Excellence. \nEmail: mason@msu.edu
URL:https://www.ieeetoronto.ca/event/cas-distinguished-lecture-augmented-perception-next-generation-wearables-and-human-machine-interfaces/
LOCATION:Virtual – Zoom
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20210331T193000
DTEND;TZID=America/Toronto:20210331T210000
DTSTAMP:20260417T075829
CREATED:20210430T023728Z
LAST-MODIFIED:20210809T204329Z
UID:10000370-1617219000-1617224400@www.ieeetoronto.ca
SUMMARY:EDS Distinguished Lecture - Self-Heating in FinFETs: Characterization\, Reliability and Impact on Logic Circuits
DESCRIPTION:The Circuits & Devices Chapter of IEEE Toronto is pleased to invite you to join us for a virtual talk by Distinguished Lecturer Dr. Durga Misra of the New Jersey Institute of Technology. \nPlease see below for schedule and details. \nTopic: Self-Heating in FinFETs: Characterization\, Reliability and Impact on Logic Circuits \nAbstract: \nDevice scaling for sub-10 nm CMOS technology has introduced bulk/SOI FinFETs This talk will outline the self-heating (SH) in FinFETs and its characterization. Local self-heating can potentially affect device performance and exacerbate the effects of some reliability mechanisms. Three different measurement methodologies for the electrical characterization of FinFET self-heating at wafer-level will be described. Also\, the impact of self-heating on reliability testing at DC conditions as well as realistic CMOS logic operating (AC) conditions will be discussed. Front-end-of-line (FEOL) reliability mechanisms\, such as hot carrier injection (HCI) and non-uniform time dependent dielectric breakdown (TDDB) will also be outlined. Self-heating is also studied at more realistic device switching conditions in logic circuits by utilizing ring oscillators with several densities and stage counts. The measurements indicate that self-heating is considerably lower in logic circuits compared to constant voltage stress conditions and degradation is not distinguishable. \nSpeaker: Prof. Durga Misra\, Department of Electrical and Computer Engineering\, New Jersey Institute of Technology \nBiography: \nProf. Durga Misra is a Professor in the Department of Electrical and Computer Engineering\, New Jersey Institute of Technology\, Newark\, USA. His current research interests are in the areas of nanoelectronic/optoelectronic devices and circuits; especially in the area of nanometer CMOS gate stacks and device reliability. He is a Fellow of IEEE and is currently a Distinguished Lecturer of IEEE Electron Devices Society (EDS) and served in the IEEE EDS Board of Governors. He is a Fellow of the Electrochemical Society (ECS). He received the Thomas Collinan Award from the Dielectric Science & Technology Division of ECS. He is also the winner of the Electronic and Photonic Division Award from ECS. He edited and co-edited more than 45 books and conference proceedings in his field of research. He has published more than 200 technical articles in peer reviewed Journals and in International Conference proceedings including 95 Invited Talks. He has graduated 19 PhD students and 40 MS students. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Waterloo\, Waterloo\, ON\, Canada\, in 1985 and 1988\, respectively.
URL:https://www.ieeetoronto.ca/event/eds-distinguished-lecture-self-heating-in-finfets-characterization-reliability-and-impact-on-logic-circuits/
LOCATION:Toronto\, Ontario Canada
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20210319T160000
DTEND;TZID=America/Toronto:20210319T173000
DTSTAMP:20260417T075829
CREATED:20210430T023727Z
LAST-MODIFIED:20210809T204232Z
UID:10000367-1616169600-1616175000@www.ieeetoronto.ca
SUMMARY:EDS Distinguished Lecture - Differentiated Fully Depleted SOI (FDSOI) technology for highly efficient and integrated mmwave 5G connectivity solution
DESCRIPTION:The Circuits & Devices Chapter of IEEE Toronto is pleased to invite you to join us for a virtual talk by Distinguished Lecturer Dr. Anirban Bandyopadhyay of Globalfoundries Inc. \nPlease see below for the schedule and details of the talk. \nTopic: Differentiated Fully Depleted SOI (FDSOI) Technology for Highly Efficient and Integrated mmwave 5G Connectivity Solution \nAbstract: \nThe emergence of enhanced mobile broadband (eMBB) connectivity based on mmwave 5G generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband\, it also poses a lot of technical challenges in terms of coverage\, generating enough transmitted power efficiently particularly in the uplink\, system cost & scaling and long term reliability of the hardware system particularly for  infrastructure including Satellite born systems. Current talk will focus on how Silicon technologies based on differentiated fully depleted SOI (FDSOI) can address the above challenges by enabling a highly efficient and integrated radio without compromising on the mmwave performance and reliability. Talk will highlight the technology Figures of Merits (FOMs) for a mmwave phased array system and how a differentiated FDSOI technology platform compares with other silicon technologies in terms of devices and circuits. \nSpeaker: Dr. Anirban Bandyopadhyay of GLOBALFOUNDRIES INC. \nBiography: \nDr. Anirban Bandyopadhyay is the Senior Directorof Strategic Applications within the Mobility & Wireless Infrastructure Business Unit of GLOBALFOUNDRIES\, USA. His work is currently focused on hardware architecture & technology evaluations for emerging RF and mmwave applications. Prior to joining GLOBALFOUNDRIES\, he was with IBM Microelectronics\, New York and with Intel\, California where he worked on different areas like RF Design Enablement\, Silicon Photonics\, signal integrity in RF & Mixed signal SOC’s. Dr. Bandyopadhyay did his PhD in Electrical Engineering from Tata Institute of Fundamental Research\, India and Post-Doctoral research at Nortel\, Canada and at Oregon State University\, USA. He represents Global Foundries in different industry consortia and alliances on RF/mmwaveapplications and is a Distinguished Lecturer of IEEE Electron Devices Society.
URL:https://www.ieeetoronto.ca/event/eds-distinguished-lecture-differentiated-fully-depleted-soi-fdsoi-technology-for-highly-efficient-and-integrated-mmwave-5g-connectivity-solution/
LOCATION:Toronto\, Ontario Canada
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20210304T140000
DTEND;TZID=America/Toronto:20210304T150000
DTSTAMP:20260417T075829
CREATED:20210430T023721Z
LAST-MODIFIED:20210501T003210Z
UID:10000356-1614866400-1614870000@www.ieeetoronto.ca
SUMMARY:CAS Distinguished Lecture - Circuit Design and Silicon Prototypes for Compute-in-Memory for Deep Learning Inference Engine
DESCRIPTION:Date & Time: March 4\, 2021\n2:00 P.M. – 3:00 P.M. \nSpeaker(s): Dr. Shimeng Yu \nLocation: Virtual \nContact: Wagih Ismail \nAbstract: Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in the deep learning inference engine. SRAM and resistive random access memory (RRAM) are identified as two promising embedded memories to store the weights of the deep neural network (DNN) models. In this seminar\, first I will review the recent progresses of SRAM and RRAM-CIM macros that are integrated with peripheral analog-to-digital converter (ADC). The bit cell variants (e.g. 6T SRAM\, 8T SRAM\, 1T1R\, 2T2R) and array architectures that allow parallel weighted sum are discussed. State-of-the-art silicon prototypes are surveyed with normalized metrics such as energy efficiency (TOPS/W). Second\, we will discuss the array-level characterizations of non-ideal device characteristics of RRAM\, e.g. the variability and reliability of multilevel states\, which may negatively affect the inference accuracy. Third\, I will discuss the general challenges in CIM chip design with regards to the imperfect device properties\, ADC overhead\, and chip to chip variations. Finally\, I will discuss future research directions including monolithic 3D integration of memory tier on top of the peripheral logic tier. \nBiography: \nShimeng Yu is currently an associate professor of electrical and computer engineering at Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009\, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013\, respectively. From 2013 to 2018\, he was an assistant professor at Arizona State University. \nProf. Yu’s research interests are the semiconductor devices and integrated circuits for energy-efficient computing systems. His research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator\, in-memory computing\, 3D integration\, and hardware security. \nAmong Prof. Yu’s honors\, he was a recipient of NSF Faculty Early CAREER Award in 2016\, IEEE Electron Devices Society (EDS) Early Career Award in 2017\, ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018\, Semiconductor Research Corporation (SRC) Young Faculty Award in 2019\, ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020\, and IEEE Circuits and Systems Society (CASS) Distinguished Lecturer for 2021-2022\, etc. \nProf. Yu served or is serving many premier conferences as technical program committee\, including IEEE International Electron Devices Meeting (IEDM)\, IEEE Symposium on VLSI Technology\, IEEE International Reliability Physics Symposium (IRPS)\, ACM/IEEE Design Automation Conference (DAC)\, ACM/IEEE Design\, Automation & Test in Europe (DATE)\, ACM/IEEE International Conference on Computer-Aided-Design (ICCAD)\, etc. He is a senior member of the IEEE. \nEmail: shimeng.yu@ece.gatech.edu
URL:https://www.ieeetoronto.ca/event/cas-distinguished-lecture-circuit-design-and-silicon-prototypes-for-compute-in-memory-for-deep-learning-inference-engine/
LOCATION:Toronto\, Ontario Canada
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20210211T145000
DTEND;TZID=America/Toronto:20210211T155000
DTSTAMP:20260417T075829
CREATED:20210430T023721Z
LAST-MODIFIED:20210501T002715Z
UID:10000351-1613055000-1613058600@www.ieeetoronto.ca
SUMMARY:Design And Analysis Of Chiplet Interfaces For Heterogeneous Systems
DESCRIPTION:On Thursday\, February 11\, 2021 at 2:50 p.m.\, Wendem Tsegaye Beyene will present the talk “Design And Analysis Of Chiplet Interfaces For Heterogeneous Systems”. \nDay & Time: Thursday\, February 11\, 2021\n2:50 p.m. – 3:50 p.m. \nSpeaker: Wendem Tsegaye Beyene \nOrganizer(s): IEEE Silicon Valley/SF Bay Area Electronics Packaging Chapter \nLocation: Virtual – Directions for connecting with the WebEx stream will be sent via email to all registrants 1-2 days prior to the event. \nContact: Durand Jarrett-Amor\, Annette Teng \nAbstract: The chiplet interface allows multiple silicon dies of various technologies and complexities to communicate efficiently using larger parallel interconnects in a single package. The second layer of interconnect on the package (silicon or organic interposer) provides dense channels as well as low impedance power delivery paths between multiple independent power domains. Although the channels are very short and the I/O power can be reduced by an order of magnitude\, the huge increase in the transient current in multiple dies and the unique clocking architecture makes the supply noise and timing jitter the limiting factors in designing high-performance multi-die systems. This talk discusses the unique signal and power integrity challenges of chiplet interfaces. \nRegister: Please visit https://eps2102.eventbrite.com to register for this event. \nBiography: Wendem Beyene received his B.S. and M.S. degrees in Electrical Engineering from Columbia University\, and his Ph.D. degree in Electrical and Computer Engineering from University of Illinois at Urbana-Champaign. In the past\, he was employed by IBM\, Hewlett-Packard\, Agilent Technologies and Rambus Inc. He also worked as a principal Engineer with Intel Corp. managing a team working on modeling and analysis of power-delivery and signaling systems of digital-core and mixed-signal I/O subsystems of FPGA chips. He is an elected Associate Fellow of the Ethiopian Academy of Sciences\, and has been selected as a Distinguished Llecturer for IEEE EPS as well as for IEEE EMCS Society.
URL:https://www.ieeetoronto.ca/event/design-and-analysis-of-chiplet-interfaces-for-heterogeneous-systems/
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20210121T210000
DTEND;TZID=America/Toronto:20210121T223000
DTSTAMP:20260417T075829
CREATED:20210430T023720Z
LAST-MODIFIED:20210501T002239Z
UID:10000343-1611262800-1611268200@www.ieeetoronto.ca
SUMMARY:JOINT EPS/CAS WEBINAR: FLEXIBLE HYBRID ELECTRONICS 2.0
DESCRIPTION:On Thursday\, January 21\, 2021 at 9:00 p.m.\, the IEEE Toronto Circuits & Devices Chapter invites you to attend a Distinguished Lecture webinar co-sponsored by the IEEE OREGON JOINT EPS/CAS CHAPTER. \nDay & Time: Thursday\, January 21\, 2021\n9:00 p.m. – 10:30 p.m. \nSpeaker: Subramanian Iyer of UCLA \nOrganizer(s): IEEE Toronto Circuits & Devices Chapter\, IEEE Oregon Joint EPS/CAS Chapter \nLocation: Virtual (Webex)\nConnect info sent to registered attendees \nContact: Mengqi Wang\, James Morris \nAbstract: In the last few years\, electronics packaging has rightfully emerged from the shadows of CMOS scaling to make a significant impact in high performance and mobile appliance computing. The area of Flexible Hybrid Electronics (FHE) has also developed and is making a significant impact in the area of medical and wellness electronics. The first generation of these devices have\, for most part\, adapted Printed Circuit Board (PCB) technology by using thinner PCBs and assembling either thinned or thin packaged “older” generation of chips on to these platforms\, typically with coarse printed wiring to connect a small number of such chips. This approach\, while immensely useful to get the field going\, needs to adapt and borrow from the both silicon and advanced packaging technology trends\, so that we can advance this trend to the next level. The key paradigm challenges ahead are: scaling the FHE in general – this includes the adoption of dielet (chiplet) technology in more advanced CMOS nodes including edge-AI\, higher performance interconnects\, flexible high-density energy storage\, wireless communication and advanced ergonomics and all of these at lower cost and higher reliability. In this talk we will address these challenges and outline a possible technology roadmap to achieve these goals in the next few years. \nRegister: Please visit https://events.vtools.ieee.org/m/256124 to register. \nBiography: \n\n\n\nSubramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT\, Salicide\, electrical fuses\, embedded DRAM and 45nm technology node used to make the first generation of truly low power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently\, he has been exploring new packaging paradigms and device innovations that they may enable wafer-scale architectures\, in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 75 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow\, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors and iMAPS. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012 and the 2020 iMAPS Daniel C. Hughes Jr Memorial award. \nList of publications/patents: https://scholar.google.com/citations?user=xXV4oIMAAAAJ&hl=en \nEmail: S.S.Iyer@ucla.edu
URL:https://www.ieeetoronto.ca/event/joint-eps-cas-webinar-flexible-hybrid-electronics-2-0/
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20181116T140000
DTEND;TZID=America/Toronto:20181116T150000
DTSTAMP:20260417T075829
CREATED:20210430T022120Z
LAST-MODIFIED:20210430T225259Z
UID:10000249-1542376800-1542380400@www.ieeetoronto.ca
SUMMARY:Photonics Integration for Applications in Astrophotonics and Quantum Information
DESCRIPTION:Friday Nov 16\, 2018 at 2:00 p.m. Mario Dagenais\, Professor in the Department of Electrical and Computer Engineering\, University of Maryland\, will be presenting “Photonics Integration for Applications in Astrophotonics and Quantum Information”. \nDay & Time: Friday November 16th\, 2018\n2:00 p.m. ‐ 3:00 p.m. \nSpeaker: Mario Dagenais\nProfessor in the Department of Electrical and Computer Engineering\, University of Maryland \nOrganizers: IEEE Toronto Circuits & Devices Chapter \nLocation: Room SF1101\n10 King’s College Rd\,\nToronto\, ON M5S 3G4 \nContact: Mengqi Wang \nAbstract: We will describe our work on optical integration on a chip\, in particular how to realize a complex waveguide Bragg grating for rejecting several emission lines from the atmosphere for astronomical observation and how to implement an integrated spectrometer based on Arrayed Waveguide Gratings (AWGs) or on echelle gratings. We will also present our work for creating an on-chip ultra-high rejection filter (> 100 dB) for applications in quantum information. \nBiography: Professor Dagenais’ research interests are in photonics integration\, high efficiency photovoltaic conversion\, and nitride optoelectronics. Professor Dagenais received his Ph.D. from the University of Rochester in 1978 working in Quantum Optics and photon correlations under the direction of Professor Mandel. Together with Jeff Kimble\, he made the first observation of photon antibunching. He was a Research Fellow at Harvard University from 1978 to 1980\, where he worked in nonlinear optics with Professor Bloembergen. From 1980 to 1987\, he worked at GTE Laboratories on photonic switching and semiconductor lasers. He joined the University of Maryland in 1987 where he has been Professor of Electrical and Computer Engineering since 1991. He has more than 300 archival and conference publications. He has co-chaired several national and international meetings. Professor Dagenais is a Fellow of the Optical Society of America\, a Fellow of IEEE\, and a Fellow of the Electromagnetic Society.
URL:https://www.ieeetoronto.ca/event/photonics-integration-for-applications-in-astrophotonics-and-quantum-information/
LOCATION:Room SF1101 10 King’s College Rd\, Toronto\, ON M5S 3G4
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20180924T140000
DTEND;TZID=America/Toronto:20180924T150000
DTSTAMP:20260417T075829
CREATED:20210430T022111Z
LAST-MODIFIED:20210430T224449Z
UID:10000233-1537797600-1537801200@www.ieeetoronto.ca
SUMMARY:Silicon Photonics: High-Density Integration for Novel Functionality
DESCRIPTION:Monday\, September 24th 2018\, Wei Jiang\, Professor in the College of Engineering and Applied Sciences at Nanjing University\, and an Associate Director of Optical Communications Systems & Network Engineering Research Center of Jiangsu Province will be presenting “Silicon Photonics: High-Density Integration for Novel Functionality”. \nDay & Time: Monday September 24th\, 2018\n2:00 p.m. ‐ 3:00 p.m. \nSpeaker: Wei Jiang\nProfessor in the College of Engineering and Applied Sciences at Nanjing University\,\nAssociate Director of Optical Communications Systems & Network Engineering Research Center of Jiangsu Province \nOrganizers: Amr S. Helmy and IEEE Toronto Circuits & Devices Chapter \nLocation: Room SFB 560\n10 King’s College Rd\,\nToronto\, ON M5S 3G4 \nContact: Mengqi Wang \nAbstract: Silicon photonics can potentially transform the photonics technology owing to its low-cost fabrication and large-scale integration advantages. Integration can open up new opportunities\, such as solid-state LIDARs for autonomous vehicles and chip-scale optical interconnects. To realize these opportunities\, reducing device size and increasing integration density will be crucial. Towards these directions\, this talk will discuss our recent experimental work on novel micro/nano-photonic structures\, including photonic crystals\, waveguide superlattices\, and free-form structures. (1) A waveguide superlattice is introduced to enable low-crosstalk\, high-density waveguide integration at half-wavelength pitches\, which opens the door to high-performance optical phased arrays\, next-generation LIDARs\, and high-density space-division multiplexing. (2) Novel free-form structures are explored to create an ultra-short waveguide “taper”. Interestingly\, the evolutionary algorithm yields an optimal structure with anomalous shapes. Through wavefront analysis\, the role of a subtle “semi-lens” is identified. (3) Further opportunities in slow-light photonic crystal switches/modulators will also be briefly discussed. In many cases\, underpinning physics needs to be fully understood first\, and then be formulated into precise theory to guide experiments and achieve viable results. \nBiography: Wei Jiang is a professor in the college of engineering and applied sciences at Nanjing University\, and an associate director of Optical Communications Systems & Network Engineering Research Center of Jiangsu Province. Prior to working at NJU\, he was an associate professor in the department of electrical and computer engineering at Rutgers\, the State University of New Jersey\, USA. His current research interests include silicon photonics\, photonic crystals\, nanophotonics\, and their applications in optical interconnects\, communications\, sensing\, and computing. He contributed to the fundamental understanding of silicon electro-optic and thermo-optic devices\, high-density waveguide integration\, slow light\, superprism effects\, and photonic crystal interface properties. He received his B.S. degree in physics from Nanjing University\, and his M.A. degree in physics and his Ph.D. degree in electrical and computer engineering from the University of Texas\, Austin. Prof. Jiang received the DARPA Young Faculty Award\, and IEEE Region I Outstanding Teaching Award\, among other honors.
URL:https://www.ieeetoronto.ca/event/silicon-photonics-high-density-integration-for-novel-functionality/
LOCATION:Room SFB 560\, 10 King’s College Rd\, Toronto\, ON M5S 3G4
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20170531T140000
DTEND;TZID=America/Toronto:20170531T150000
DTSTAMP:20260417T075829
CREATED:20210430T012916Z
LAST-MODIFIED:20210430T211608Z
UID:10000060-1496239200-1496242800@www.ieeetoronto.ca
SUMMARY:InAs Quantum Dot Micro-disk Lasers Grown on Exact (001) Si Emitting at Communication Wavelengths
DESCRIPTION:Wednesday May 31\, 2017 at 2:10 p.m. Kei May Lau\, Fang Professor of Engineering and Chair Professor at the Hong Kong University of Science and Technology will be presenting “InAs Quantum Dot Micro-disk Lasers Grown on Exact (001) Si Emitting at Communication Wavelengths”. \nDay & Time: Wednesday May 31\, 2017\n2:10 p.m. – 3:00 p.m. \nSpeaker: Kei May Lau\nFang Professor of Engineering and Chair Professor\nDepartment of Electronic and Computer Engineering\nHong Kong University of Science and Technology \nLocation: Room BA 1220\n40 St. George Street\nToronto\, ON M5S 2E4 \nContact: Junho Jeong \nOrganizers: IEEE Toronto Photonics Society \nAbstract: To support an energy-efficient optical interconnect technology enabled by silicon photonics\, development of low-energy-consumption active devices and the corresponding integration technology is needed. Most communication wavelength lasers with excellent device performance have been grown on III-V substrates and bonded to silicon. For integration\, there are considerable advantages in a technology that allow growth and fabrication of such lasers on III-V/ Si compliant substrates. Quantum dot (QD) active layers grown on lattice-matched substrates have already shown their capability for lasers with low-threshold densities and temperature-independent operation. In addition\, the reduced sensitivity of QD to defects and their unique capability of filtering dislocations make them an ideal candidate as the gain medium of hetero-integrated III-V on Si optical sources. In this talk\, I will discuss the growth of multi-stack QDs on compliant substrates by MOCVD. Fabrication and laser characteristics of whispering-gallery-mode (WGM) micro-disk lasers using the grown epitaxial structures will also be discussed. Initial demonstration was achieved using simple a colloidal lithography process in combination with dry and wet-etching. The micro-disk lasers were one to four microns in diameter\, with single mode lasing at either 1.3 or 1.55 μm\, depending on the barrier/cladding system. With smooth sidewalls and sufficient undercut by wet etching of the pedestal\, the air-cladded MDs exhibit ultra-low thresholds of a few mW by optical pumping. Preliminary results of electrically-pumped micro-lasers will also be presented. These energy-efficient microlasers are excellent candidates for on-chip integration with silicon photonics. \nBiography: Professor Kei May Lau is Fang Professor of Engineering at the Hong Kong University of Science and Technology (HKUST). She received the B.S. and M.S. degrees in physics from the University of Minnesota\, Minneapolis\, and the Ph.D. degree in Electrical Engineering from Rice University\, Houston\, Texas. She was on the ECE faculty at the University of Massachusetts/Amherst and initiated MOCVD\, compound semiconductor materials and devices programs. Since the fall of 2000\, she has been with the ECE Department at HKUST. She established the Photonics Technology Center for R&D effort in III-V materials\, optoelectronic\, high power\, and high-speed devices. Professor Lau is a Fellow of the IEEE\, and a recipient of the US National Science Foundation (NSF) Faculty Awards for Women (FAW) Scientists and Engineers (1991) and Croucher Senior Research Fellowship (2008). She is an Editor of the IEEE EDL and Associate Editor of Applied Physics Letters.
URL:https://www.ieeetoronto.ca/event/inas-quantum-dot-micro-disk-lasers-grown-on-exact-001-si-emitting-at-communication-wavelengths/
LOCATION:Room BA 1220 40 St. George Street\, Toronto\, ON M5S 2E4
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20170120T140000
DTEND;TZID=America/Toronto:20170120T150000
DTSTAMP:20260417T075829
CREATED:20210430T002611Z
LAST-MODIFIED:20210430T005139Z
UID:10000096-1484920800-1484924400@www.ieeetoronto.ca
SUMMARY:CMOS Bioelectronics
DESCRIPTION:Friday January 20\, 2017 at 2:10 p.m. Professor Ken Shepard\, Electrical and Biomedical Engineering at Columbia University\, will be presenting “CMOS Bioelectronics”. \nSpeaker: Prof. Ken Shepard\nElectrical and Biomedical Engineering\nColumbia University \nDay & Time: Friday\, January 20th\, 2017\n2:10 pm – 3:00 pm \nLocation: Room GB 248\, 35 St George St\, Toronto\, ON M5S 1A4 \nContact: Junho Jeong \nOrganizer: IEEE Toronto Photonics Chapter \n**Refreshments will be served** \nAbstract: CMOS electronics\, which has revolutionized communications and computation in the last 30 years\, has the same transformative potential for life science applications with appropriate “more than Moore” augmentation. In this talk\, we will outline work in my group over the last 10 years\, which has applied augmented CMOS to problems in molecular diagnostics\, microbiology\, and neuroscience. We will discuss several on-going projects in my group in these areas include high-bandwidth CMOS-integrated nanopores\, point-functionalized nanotube devices integrated on CMOS for genomic diagnostics\, electrochemical imaging chips for understanding microbial communities\, high-density electrophysiological arrays for in vivo and in vitro studies of neural systems\, biologically powered solid-state electronics\, and various wireless probes to studying neural and cellular systems. \nBiography: Ken Shepard received the B.S.E. degree from Princeton University\, Princeton\, NJ\, in 1987 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University\, Stanford\, CA\, in 1988 and 1992\, respectively. From 1992 to 1997\, he was a Research Staff Member and Manager with the VLSI Design Department\, IBM T. J. Watson Research Center\, Yorktown Heights\, NY\, where he was responsible for the design methodology for IBM’s G4 S/390 microprocessors. Since 1997\, he has been with Columbia University\, New York\, where he is now the Lau Familty Professor of Electrical Engineering and Biomedical Engineering. He also was Chief Technology Officer of CadMOS Design Technology\, San Jose\, CA\, until its acquisition by Cadence Design Systems in 2001. He is current serving on the board of two other start-ups\, Ferric\, commercializing integrated voltage regulator technology\, and Quicksilver\, commercializing single-molecule electronic genomic diagnostics. His current research interests include power electronics\, carbon-based devices and circuits\, and CMOS bioelectronics.
URL:https://www.ieeetoronto.ca/event/cmos-bioelectronics/
LOCATION:Room GB 248\, 35 St George St\, Toronto\, ON M5S 1A4
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20160624T110000
DTEND;TZID=America/Toronto:20160624T120000
DTSTAMP:20260417T075829
CREATED:20210429T230403Z
LAST-MODIFIED:20210430T001520Z
UID:10000055-1466766000-1466769600@www.ieeetoronto.ca
SUMMARY:Quantum-confined oxide heteronanostructures: Low-cost design\, electronic structure\, interfacial properties & device applications for solar energy conversion
DESCRIPTION:June 24\, 2016 at 11:10 a.m. Professor Lionel Vayssieres\, of Xi’an Jiaotong University\, will be presenting “Quantum-confined oxide heteronanostructures: Low-cost design\, electronic structure\, interfacial properties & device applications for solar energy conversion”. \nSpeaker: Professor Lionel Vayssieres\nInternational Research Center for Renewable Energy (IRCRE)\, Xi’an Jiaotong University \nDay & Time: Friday\, June 24\, 2016\n11:10 a.m. – 12:00 p.m. \nLocation: Room BA 1200\n40 St George St\, Toronto\, ON M5S 2E4 \nContact: Junho Jeong \nRefreshments will be served prior to the lecture. \nAbstract: Given that conventional technologies which attempt to improve the performance of existing materials and devices for solar energy conversion and solar fuels generation by further development along the same incremental approach are reaching their limits\, it is crucial to develop novel materials where bulk limitations are overcome by changing the fundamental underlying physics and chemistry\, by e.g. nanostructuring design and quantum confinement effects. As important is a comprehensive fundamental and applied knowledge of their interfacial properties and electronic structure in relation with their structural and optical properties to quantitatively optimize their efficiency. Our strategy to address such crucial requirements is to fabricate materials and devices based on metal oxide (hetero)nanostructures consisting of surface chemistry-controlled quantum dots and rods building-blocks utilizing low-cost and large scale aqueous chemical growth. The electronic structure and structural\, optical\, and photoelectrochemical properties of such novel visible light-active oxide semiconductors based on vertically oriented quantum rod-arrays have been thoroughly investigated at synchrotron radiation facilities by X-ray spectroscopies. Direct correlation between dimensionality and surface chemistry\, bandgap and band edges\, orbital character and symmetry\, surfaces states\, electrical and defect properties have been unraveled and will be demonstrated on various oxide structures of high relevance for this field. An overview of decades of achievements as well as recent advances in novel materials design strategy will be demonstrated along with the latest breakthrough in highly efficient structure for low cost solar hydrogen generation by direct water splitting at neutral pH using the largest free natural resources on Earth\, e.g. the Sun and seawater. \nBiography: Born in 1968\, Prof. Vayssieres obtained a MSc in Physical Chemistry in 1990 and a PhD in Inorganic Chemistry in 1995 from the Université Pierre et Marie Curie\, Paris\, France for his research work on the Interfacial & thermodynamic growth control of metal oxide nanoparticles in aqueous solutions. He has been invited as a visiting scientist at: UT Austin; the UNESCO Centre for Macromolecules & Materials\, Stellenbosch University and iThemba LABS\, South Africa; the Glenn T. Seaborg Center\, Chemical Sciences Division\, at Lawrence Berkeley National Laboratory; Texas Materials Institute; The Ecole Polytechnique Fédérale de Lausanne\, Switzerland; the University of Queensland\, Australia\, and Nanyang Technological University\, Singapore. He was an independent scientist at the National Institute for Materials Science (NIMS)\, Tsukuba\, Japan for 8 years. He has authored 100+ publications in major international journals and book series cited 9150+ times since the year 2000 (4500+ since 2011\, Google Scholar); Top 1% Scientists in Materials Science (Thomson Reuters). All time 8 ESI Highly Cited papers (5 as first and corresponding author) in Materials Science\, Chemistry\, Physics\, and Environment/Ecology. He has given 344 talks in 30 countries: 166 lectures at international conferences/workshops (45 plenary/keynote\, 98 invited\, 21 contributed\, 2 tutorials) including one of the last MRS Spring Symposium X lecture held in San Francisco in 2015 as well as 178 seminars at universities\, governmental and/or industrial research institutes. He is currently a full time 1000-Talent Professor\, co-founder and scientific director of the International Research Center for Renewable Energy (IRCRE) at Xi’an Jiaotong University\, China as well as\, since 2003\, a guest scientist at the Chemical Sciences Division at Berkeley National Lab and the founding editor-in-chief of the International Journal of Nanotechnology.
URL:https://www.ieeetoronto.ca/event/quantum-confined-oxide-heteronanostructures-low-cost-design-electronic-structure-interfacial-properties-device-applications-for-solar-energy-conversion/
LOCATION:BA 1200\, 40 St George Street\, Toronto
CATEGORIES:Circuits & Devices
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/Toronto:20160229T150000
DTEND;TZID=America/Toronto:20160229T160000
DTSTAMP:20260417T075829
CREATED:20210429T230400Z
LAST-MODIFIED:20210430T000610Z
UID:10000011-1456758000-1456761600@www.ieeetoronto.ca
SUMMARY:Photonics for Microwave Systems and Ultra-Wideband Signal Processing
DESCRIPTION:Monday February 29th\, 2016 at 3:10 p.m. Professor Willie Ng\, Dept. of Electrical Engineering\, University of Southern California\, will be presenting “Photonics for Microwave Systems and Ultra-Wideband Signal Processing”. \nSpeaker: Professor Willie Ng\nDept. of Electrical Engineering\, University of Southern California\nIEEE Fellow \nDay & Time: Monday\, February 29th\, 2016\n3:10 p.m. – 4:00 p.m. \nLocation: GB 120\, Galbraith Building\, University of Toronto\n35 St George St\, Toronto\, ON M5S 1A4 \n**Refreshments will be served** \nContact: Junho Jeong \nAbstract: This seminar will describe the development and application of photonics technology in microwave antenna systems and ultra-wideband signal processing. It will cover our recent work on the characterization of high frequency modulators and mode-locked lasers\, photonic-assisted analog-to-digital conversion\, as well as RF-photonic filtering. The seminar will also describe how the broadband capabilities of photonics and wavelength division multiplexed (WDM) technologies can be utilized for high dynamic range antenna remoting and true-time-delay beamforming that cover multiple microwave bands. \nBiography: Dr. Willie W. Ng is currently a Research Professor ofl Engineering at the University of Southern California (USC). Prior to joining USC in 2013\, he spent close to three decades at HRL Laboratories\, Malibu\, CA\, where he was a Principal Research Scientist\, Program Manager and Department Manager. Under DARPA and U.S. Air Force sponsorships\, he led HRL teams that demonstrated a variety of photonic devices/subsystems designed for microwave antenna systems and ultra-wideband signal processing\, including RF-photonic filtering and photonics-assisted analog-to-digital conversion. He has given many invited talks in IEEE/OSA Conferences and DARPA Symposiums\, and is the author and co-author of over 100 journal articles and conference papers. He holds 26 U.S. patents in the area of photonics technology\, with many pending. Cited for pioneering contributions to microwave photonics\, he was one of six individuals selected to receive the Excellence in Technology Award in 2005 from the Raytheon Company. Prior to HRL\, he was a Member of the Technical Staff at the Rockwell Science Center\, Thousand Oaks\, Calif.\, where he developed GaInAsP/InP buried heterostructure lasers and power converters. He received his B.S. degree in Electrical Engineering from Case Western Reserve University (Cleveland\, Ohio)\, and his M.S. and Ph.D. degrees in Electrical Engineering from the California Institute of Technology (Pasadena\, Calif.) under the guidance of Prof. A. Yariv. His thesis work was on the demonstration of GaAlAs/GaAs Distributed Bragg Reflector lasers and Bragg waveguides. He is a fellow of the IEEE\, and serves on the 2013-2015 CLEO (Conference on Lasers and Electro-Optics) Technical Committee.
URL:https://www.ieeetoronto.ca/event/photonics-for-microwave-systems-and-ultra-wideband-signal-processing/
LOCATION:GB 120\, University of Toronto
CATEGORIES:Circuits & Devices
END:VEVENT
END:VCALENDAR