BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//IEEE Toronto Section - ECPv6.15.17//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://www.ieeetoronto.ca
X-WR-CALDESC:Events for IEEE Toronto Section
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20210314T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20211107T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20220313T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20221106T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221121T160000
DTEND;TZID=America/New_York:20221121T170000
DTSTAMP:20260417T193956
CREATED:20221121T174553Z
LAST-MODIFIED:20221121T174554Z
UID:10000586-1669046400-1669050000@www.ieeetoronto.ca
SUMMARY:LMAG Chair Teleconference Agenda 2022-Nov-21 4:00 PM (EST)
DESCRIPTION:R7 LMAG MONTHLY MEETING\nOakville\, Ontario\, Canada\, L6H 2B1\, Virtual: https://events.vtools.ieee.org/m/333503
URL:https://www.ieeetoronto.ca/event/lmag-chair-teleconference-agenda-2022-nov-21-400-pm-est/
LOCATION:Oakville\, Ontario\, Canada\, L6H 2B1\, Virtual: https://events.vtools.ieee.org/m/333503
END:VEVENT
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20221121T180000
DTEND;TZID=America/New_York:20221121T193000
DTSTAMP:20260417T193956
CREATED:20221112T164712Z
LAST-MODIFIED:20230402T175428Z
UID:10000584-1669053600-1669059000@www.ieeetoronto.ca
SUMMARY:IEEE EDS Distinguished Lecture: Low Power Design and Predictive Failure Analytics in Silicon in nm Era
DESCRIPTION:Power has become the key driving force in processor as well AI specific accelerator designs as the frequency scale-up is reaching saturation. In order to achieve low power system\, circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale VLSI circuits. Achieving low power and high performance simultaneously is always difficult. Technology has seen major shifts from bulk to SOI and then to non-planar devices such as FinFET and Trigates.\nThis talk consists of pros and cons analysis on technology from power perspective and various techniques to exploit lower power. As the technology pushes towards sub-7nm era\, process variability and geometric variation in devices can cause variation in power. The reliability also plays an important role in the power-performance envelope. This talk also reviews the methodology to capture such effects and describes all the power components. All the key areas of low power optimization such as reduction in active power\, leakage power\, short circuit power and collision power are covered. Usage of clock gating\, power gating\, longer channel\, multi-Vt design\, stacking\, header-footer device techniques and other methods are described for logic and memory used for processors and AI. Finally the talk summarizes key challenges in achieving low power.\nIn addition the tutorial gives a brief overview of predictive failure analytics used in nm Technology. Process and environmental variations impact circuit behavior it is important to model their effects to build robust circuits. The tutorial describe how key statistical techniques can be effectively used to analyze and build robust circuits.\nSpeaker(s): Dr. Rajiv Joshi\,\nAgenda:\nThe event will start at 18:00PM EST and the talk will start at 18:10PM EST.\nRoom: BA2155\, Bldg: Bahen Centre for Information Technology\, 40 St George St \, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/331087
URL:https://www.ieeetoronto.ca/event/low-power-design-and-predictive-failure-analytics-in-silicon-in-nm-era/
LOCATION:Room: BA2155\, Bldg: Bahen Centre for Information Technology\, 40 St George St \, Toronto\, Ontario\, Canada\, M5S 2E4\, Virtual: https://events.vtools.ieee.org/m/331087
CATEGORIES:Circuits & Devices,Solid-State Circuits
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END:VCALENDAR