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C/ID: A Design Methodology for Implementing Nanoscale Analog FET Circuits.

Friday, June 3, 2022 @ 4:00 PM - 5:00 PM

Most of the existing circuit design methodologies are based on iterative methods, which are very time consuming and sometimes far from being optimal. The process of analog circuit design is generally so complex that most designers rely mainly on their own intuition to design and move toward an acceptable design point, which in many cases is based on a long process of trial-and-errors. There are two dominant circuit design methodologies used in academic institutions and industry: (1) Inversion-Coefficient (IC) method, and (2) Gm/IDS (GmID) approach. While IC method is more analytical, GmID require extensive device characterizations in order to create a comprehensive data-base describing device behavior in all modes of operations for different device sizes. Meanwhile, designers need to develop their own optimization scripts to search through all possible design points and select the best fit for their application, as these methodologies are not supported by the common EDA Tools.

In this seminar, an improved design methodology will be introduced, which lies somewhere between the two approaches. Called C/IDS, the proposed design methodology requires prior knowledge on only few technology-dependent parameters, which are very easy to extract. Due to its analytical nature, this approach provides comprehensive design insight, while the flow of design can be automatized easily. Several examples will be provided to show effectiveness of the proposed algorithm for implementing energy and power efficient circuits. A set of data points demonstrating how performance of analog circuits evolve with technology scaling will be provided.

Speaker(s): Armin Tajalli

Register: https://events.vtools.ieee.org/m/314527

Biography:Armin Tajalli received his B.S. from Sharif University of Technology, Tehran, Iran, and the Ph.D. from Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland. He was part of the initiating team and a Senior Analog Architect with Kandou Bus, Lausanne, Switzerland, where he is currently the lead of the R&D Department. Since December 2017, he has joined as an Assistant Professor to the University of Utah, Salt Lake City, USA. He has published more than 90 articles in peer reviewed journals and conferences and holds 40 patents. He has received several awards, including The Best Paper Award in DesignCon (2016), PhD Prime Award at EPFL, Switzerland (2010), and IEEE AMD/CICC Scholarship (2009). He is currently serving as a Technical Program Committee (TPC) Member in IEEE CICC and ESSCIRC, and an Associate Editor of the IEEE Transactions on VLSI Systems.

Details

Date:
Friday, June 3, 2022
Time:
4:00 PM - 5:00 PM
Event Category:

Organizer

Wagih Ismail
Email:
wagih.ismail@ieee.org

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