(Feb 06) Fiber Attach: Technical Progress Within IEEE Standards

The IEEE Photonics Society / Standards Committee recently published a whitepaper on Fiber Attach.  Transmission of light between or in and out of any photonic platform normally requires attachment to a fiber that is used as a flexible optical waveguide.  An effective fiber attach involves many requirements and metrics that have so far involved decades of research.  The presentation will cover the whitepaper in detail, some technical background, the path forward, and how to become involved.

Speaker: John S. Mazurowski of Penn State Applied Research Laboratory

View the poster:

(Apr 04) The Origins of Silicon Valley: Lessons for Entrepreneurs, Startups, and Technology Hubs

Silicon Valley is commonly acknowledged as the tech capital of the world.  How did Silicon Valley come into being, and what can we learn?  The story goes back to local Hams trying to break RCA’s tube patents, Stanford “angel” investors, the sinking of the Titanic, WW II and radar, and the SF Bay Area infrastructure that developed – these factors pretty much determined that the semiconductor and IC industries would be located in the Santa Clara Valley, and that the Valley would remain the world’s innovation center as new technologies emerge, and be the model for innovation worldwide.
This talk will give an exciting and colorful history of development and innovation that began in Palo Alto in 1909.  You’ll meet some of the colorful characters – Cyril Elwell, Lee De Forest, Bill Eitel, Charles Litton, Fred Terman, David Packard, Bill Hewlett, Bill Shockley and others – who came to define our worldwide electronics industries through their inventions and process development.  You’ll understand some of the novel management approaches that have become the hallmarks of its tech startups.  Many of these attributes can be found in other technology hubs; however, the SF Bay Area has five generations of experience, as well as a “critical mass” of talent, making it difficult for others to catch up.  In this talk, the key attributes will be illustrated and analyzed, for consideration by other tech hubs, and for entrepreneurs interested in creating their own start-ups or understanding them.

Speaker: Paul Wesling, IEEE Fellow

Link to video recording: https://ieeetv.ieee.org/video/successful-tech-hubs-silicon-valley-lessons-for-toronto

Link to slides:  https://pwesling.com/docs/2404-ut.pdf 

View the gallery:

(Oct 05) Noise-Shaping SAR ADCs: From Discrete Time to Continuous Time

Noise-Shaping (NS) SAR ADCs become popular recently thanks to their low-power and high-resolution features. This presentation first summarizes and benchmarks different discrete-time (DT) NS-SAR implementations in literature. An open-loop duty-cycled residue amplifier is selected as a power-efficient solution to realize high residue gain. Then, a digital-predicted mismatch error shaping technique is introduced to improve the DAC linearity. The proposed DT NS-SAR ADC achieves 80 dB SNDR, 98 dB SFDR in a 31.25 kHz bandwidth while consuming 7.3 μW. Next, the NS-SAR architecture is extended from DT operation to continuous-time (CT) operation. The ADC sampling switch is removed and the loop filter is duty cycled to realize the CT NS-SAR operation. Compared to DT designs, the CT NS-SAR ADC is easy to drive and has inherent anti-aliasing function. As a proof of concept, the proposed CT NS-SAR ADC achieves 77 dB SNDR, 86 dB SFDR a 62.5 kHz bandwidth with a power consumption of 13.5 μW.

Speaker: Professor Pieter Harpe of Eindhoven University of Technology

Link to the pdf: noise-shaping-SAR-ADCS-event-poster.pdf

(Nov 22) IEEE EDS Distinguished Lecture: Low Power Design and Predictive Failure Analytics in Silicon in nm Era

Power has become the key driving force in processor as well AI specific accelerator designs as the frequency scale-up is reaching saturation. In order to achieve low power system, circuit and technology co-design is essential. This talk focuses on related technology and important circuit techniques for nanoscale VLSI circuits… (Read more)

Video recording of this talk can be made available to attendees of the event. If you would like to request access to this file please send an email to wagih.ismail@ieee.org.

View the poster:

(Nov 16) Energy-Efficient Designs assisted by SAR ADCs

Since late 2000’s, SAR ADCs have become one of the most popular ADC architectures showing not only excellent energy efficiency but also competitive conversion speed owing to the digital-friendly compact structure and architectural evolution in deep submicron technologies… (Read more)

(Oct 14) CASS Toronto: Current Trends, Future Directions, and Career Opportunities in Electronics and Circuits

This event features representatives from prominent companies with offices in the GTA to give talks on active areas of innovation in the circuits & electronics industry. These sessions will help familiarize students with where companies are most actively focussing innovation efforts… (Read more)

View the gallery:

(Jun 22) Overview of Secondary Surveillance Radar (SSR) and Identification Friend/Foe (IFF) Systems – Part I – Virtual Lecture – CEU/PDH Available

The lecture is composed of two one-hour parts. In Part I a general overview of SSR/IFF is presented which includes a review of terms and definitions. From there, a historical timeline of SSR/IFF is summarized beginning with early implementations and ending with modern day systems… (Read more)

(May 21) The Analog Designer’s Toolbox (ADT): Towards A New Paradigm for Analog IC Design

The integrated circuit (IC) technology has witnessed an exponential advancement in the last decades and has changed every aspect in our life. On the other hand, the analog IC design flow did not experience any major change since the introduction of Berkeley SPICE in the 1970s, posing significant challenges… (Read more)

(Apr 16) CAS Distinguished Lecture – Augmented Perception: Next Generation Wearables and Human-Machine Interfaces

Products like Fitbit and the Apple Watch have brought to the public decades of foundational work on wearable technologies achieved by researchers in the IEEE CAS Society and related groups. Similarly, research into brain- and human-machine interface is starting to enter the public domain in applications… (Read more)

(Mar 31) EDS Distinguished Lecture – Self-Heating in FinFETs: Characterization, Reliability and Impact on Logic Circuits

Device scaling for sub-10 nm CMOS technology has introduced bulk/SOI FinFETs This talk will outline the self-heating (SH) in FinFETs and its characterization. Local self-heating can potentially affect device performance and exacerbate the effects of some reliability mechanisms… (Read more)

(Mar 19) EDS Distinguished Lecture – Differentiated Fully Depleted SOI (FDSOI) technology for highly efficient and integrated mmwave 5G connectivity solution

The emergence of enhanced mobile broadband (eMBB) connectivity based on mmwave 5G generated huge interest in the entire telecommunication ecosystem. While mmwave allows huge bandwidth of channels to enable enhanced broadband, it also poses a lot of technical challenges in terms of coverage… (Read more)

(Mar 4) Circuit Design and Silicon Prototypes for Compute-in-Memory for Deep Learning Iinference Engine

Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in the deep learning inference engine. SRAM and resistive random access memory (RRAM) are identified as two promising embedded memories to store the weights of the deep neural network (DNN) models… (Read more)

(Feb 11) EPS Distinguished Lecture Co-Hosted with Santa Clara Valley Area Chapter of the EPS: Design And Analysis Of Chiplet Interfaces For Heterogeneous Systems

The chiplet interface allows multiple silicon dies of various technologies and complexities to communicate efficiently using larger parallel interconnects in a single package. The second layer of interconnect on the package (silicon or organic interposer) provides dense channels as well as low impedance power… (Read more)

(Jan 21) JOINT EPS/CAS WEBINAR: FLEXIBLE HYBRID ELECTRONICS 2.0

In the last few years, electronics packaging has rightfully emerged from the shadows of CMOS scaling to make a significant impact in high performance and mobile appliance computing. The area of Flexible Hybrid Electronics (FHE) has also developed and is making a significant impact… (Read more)